Synthesis Under Yosys

[redpanda3]

Dear developers,

I faced some problems in the synthesis step:

In the build/hw/syn/yosys

3.141. Executing AST frontend in derive mode using pre-parsed AST for module \VX_fpu_sqrt'. Parameter \NUM_LANES = 4 Parameter \TAG_WIDTH = 1 Generating RTLIL representation for module$paramod$02ebeaaba3aa0519d7f252fbf0c762a441a16060\VX_fpu_sqrt'. project.v:24131: ERROR: Can't resolve task name `\dpi_fsqrt'. make: *** [Makefile:87: build] Error 1

Seems to be a dpi-c module. Could you please have a check on that?

Best, redpanda

[redpanda3]

I've commented on those lines using dpi modules for the moment.

[tinebp]

you can use yosys as follows:

PREFIX=build_base make -C hw/syn/yosys clean PREFIX=build_base CONFIGS="-DDPI_DISABLE -DEXT_F_DISABLE" make -C hw/syn/yosys synthesis