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vproc / vicuna

RISC-V Zve32x Vector Coprocessor
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Error in Questasim Simulation #114

Open aaqdas opened 1 year ago

aaqdas commented 1 year ago

Fatal: Unexpected signal: 11. /# //wsl.localhost/Ubuntu-20.04/home/aqdas/vicuna/sim/../rtl/vproc_mul_block.sv(1): Vopt Compiler exiting