vproc / vicuna

RISC-V Zve32x Vector Coprocessor
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Fix CI #116

Open PhilippvK opened 1 year ago

PhilippvK commented 1 year ago

One CI job (unit (elem, cv32e40x)) is still failing but AFAIK this was already an issue a year ago:

[23702] %Error: vproc_core_sva.svh:22: Assertion failed in TOP.vproc_top.v_core: attempt to commit instruction ID 3, which already had a commit transaction
%Error: /home/runner/work/vicuna/vicuna/sim//../sva//vproc_core_sva.svh:22: Verilog $stop