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vproc / vicuna

RISC-V Zve32x Vector Coprocessor
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Machine mode CSRs not accessible with Ibex host core when using Vicuna's verilated model #118

Open AnjaliVerma1314 opened 1 year ago

AnjaliVerma1314 commented 1 year ago

Unable to get the cycle count by reading a machine mode CSR (mcycle) on verilated model of Vicuna with Ibex host core. The machine mode CSRs seem to be not accessible with Ibex host core on Vicuna's verilator.

aaqdas commented 10 months ago

I am facing a similar problem. It declares it illegal instruction.

Update: I just remembered this issue, from the time I ran some simulations earlier. In the folder /sim, when you run the command make verilator, you need to run make verilator CORE=cv32e40x which uses the core cv32e40x instead of ibex. This resolves the problem