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vroland / epdiy

EPDiy is a driver board for affordable e-Paper (or E-ink) displays.
https://vroland.github.io/epdiy-hardware/
GNU Lesser General Public License v3.0
1.37k stars 190 forks source link

Epdiy S3 board discussion #207

Closed mcer12 closed 1 year ago

mcer12 commented 1 year ago

Since @vroland resumed work on the S3 board, let's throw ideas and notes about the schematic first, then the pcb layout and features. Don't discuss this on slack because the conversation will get lost!

lanistor commented 1 year ago

@martinberlin Yeah, i did the settings according to the wiki, here is the full log and the board picture: 

SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce3818,len:0x187c
load:0x403c9700,len:0x4
load:0x403c9704,len:0xda4
load:0x403cc700,len:0x3130
entry 0x403c9934
I (31) boot: ESP-IDF v5.1-476-g3187b8b326 2nd stage bootloader
I (31) boot: compile time Aug  7 2023 10:33:30
I (32) boot: Multicore bootloader
I (36) boot: chip revision: v0.1
I (40) qio_mode: Enabling default flash chip QIO
I (45) boot.esp32s3: Boot SPI Speed : 80MHz
I (50) boot.esp32s3: SPI Mode       : QIO
I (54) boot.esp32s3: SPI Flash Size : 4MB
I (59) boot: Enabling RNG early entropy source...
I (64) boot: Partition Table:
I (68) boot: ## Label            Usage          Type ST Offset   Length
I (75) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (83) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (90) boot:  2 factory          factory app      00 00 00010000 00177000
I (98) boot: End of partition table
I (102) esp_image: segment 0: paddr=00010020 vaddr=3c030020 size=d59d0h (874960) map
I (243) esp_image: segment 1: paddr=000e59f8 vaddr=3fc93900 size=02858h ( 10328) load
I (245) esp_image: segment 2: paddr=000e8258 vaddr=40374000 size=07dc0h ( 32192) load
I (255) esp_image: segment 3: paddr=000f0020 vaddr=42000020 size=21364h (136036) map
I (278) esp_image: segment 4: paddr=0011138c vaddr=4037bdc0 size=07ac4h ( 31428) load
I (291) boot: Loaded app from partition at offset 0x10000
I (291) boot: Disabling RNG early entropy source...
I (302) cpu_start: Multicore app
E (302) quad_psram: PSRAM ID read error: 0x00ffffff, PSRAM chip not found or not supported, or wrong PSRAM line mode
E (306) cpu_start: Failed to init external RAM!

abort() was called at PC 0x4037564c on core 0
0x4037564c: call_start_cpu0 at /Users/Shared/B/SDK/esp/esp-idf/components/esp_system/port/cpu_start.c:466 (discriminator 3)

Backtrace: 0x40375a9a:0x3fceb220 0x4037bfa5:0x3fceb240 0x403818b2:0x3fceb260 0x4037564c:0x3fceb2d0 0x403cda98:0x3fceb340 0x403cde91:0x3fceb380 0x403c999d:0x3fceb4b0 0x40045c01:0x3fceb570 |<-CORRUPTED
0x40375a9a: panic_abort at /Users/Shared/B/SDK/esp/esp-idf/components/esp_system/panic.c:452

0x4037bfa5: esp_system_abort at /Users/Shared/B/SDK/esp/esp-idf/components/esp_system/port/esp_system_chip.c:84

0x403818b2: abort at /Users/Shared/B/SDK/esp/esp-idf/components/newlib/abort.c:38

0x4037564c: call_start_cpu0 at /Users/Shared/B/SDK/esp/esp-idf/components/esp_system/port/cpu_start.c:466 (discriminator 3)

0x40045c01: ets_run_flash_bootloader in ROM
huming2207 commented 1 year ago

E (302) quad_psram: PSRAM ID read error: 0x00ffffff, PSRAM chip not found or not supported, or wrong PSRAM line mode

What's your PSRAM config? That looks like PSRAM is dead, not present or misconfigured?

lanistor commented 1 year ago

E (302) quad_psram: PSRAM ID read error: 0x00ffffff, PSRAM chip not found or not supported, or wrong PSRAM line mode

What's your PSRAM config? That looks like PSRAM is dead, not present or misconfigured?

Here is my config:

martinberlin commented 1 year ago

Wrong! Is OCTAL Mode PSRAM, not Quad mode, I wrote it in the WiKi but also here @lanistor You need to really focus and be aware on the details here when you read an explanation on how to configure this. If it's not that then it must be the S3 module that is different please post exactly what part you got soldered there. Here a side to side comparison S3-comparison

lanistor commented 1 year ago

Wrong! Is OCTAL Mode PSRAM, not Quad mode, I wrote it in the WiKi but also here @lanistor You need to really focus and be aware on the details here when you read an explanation on how to configure this. If it's not that then it must be the S3 module that is different please post exactly what part you got soldered there. Here a side to side comparison S3-comparison

Thanks, i fix this error by set OCTAL Mode, but i got a new error EPD_DRAW_LOOKUP_NOT_IMPLEMENTED, here is the log:

I (31) boot: ESP-IDF v5.1-476-g3187b8b326 2nd stage bootloader
I (31) boot: compile time Aug  7 2023 10:33:30
I (31) boot: Multicore bootloader
I (36) boot: chip revision: v0.1
I (39) qio_mode: Enabling default flash chip QIO
I (45) boot.esp32s3: Boot SPI Speed : 80MHz
I (50) boot.esp32s3: SPI Mode       : QIO
I (54) boot.esp32s3: SPI Flash Size : 4MB
I (59) boot: Enabling RNG early entropy source...
I (64) boot: Partition Table:
I (68) boot: ## Label            Usage          Type ST Offset   Length
I (75) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (83) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (90) boot:  2 factory          factory app      00 00 00010000 00177000
I (98) boot: End of partition table
I (102) esp_image: segment 0: paddr=00010020 vaddr=3c030020 size=d5a30h (875056) map
I (243) esp_image: segment 1: paddr=000e5a58 vaddr=3fc94300 size=02c08h ( 11272) load
I (245) esp_image: segment 2: paddr=000e8668 vaddr=40374000 size=079b0h ( 31152) load
I (255) esp_image: segment 3: paddr=000f0020 vaddr=42000020 size=21360h (136032) map
I (278) esp_image: segment 4: paddr=00111388 vaddr=4037b9b0 size=08858h ( 34904) load
I (291) boot: Loaded app from partition at offset 0x10000
I (292) boot: Disabling RNG early entropy source...
I (303) cpu_start: Multicore app
I (303) octal_psram: vendor id    : 0x0d (AP)
I (304) octal_psram: dev id       : 0x02 (generation 3)
I (307) octal_psram: density      : 0x03 (64 Mbit)
I (312) octal_psram: good-die     : 0x01 (Pass)
I (317) octal_psram: Latency      : 0x01 (Fixed)
I (323) octal_psram: VCC          : 0x01 (3V)
I (328) octal_psram: SRF          : 0x01 (Fast Refresh)
I (334) octal_psram: BurstType    : 0x01 (Hybrid Wrap)
I (339) octal_psram: BurstLen     : 0x01 (32 Byte)
I (345) octal_psram: Readlatency  : 0x02 (10 cycles@Fixed)
I (351) octal_psram: DriveStrength: 0x00 (1/1)
I (357) MSPI Timing: PSRAM timing tuning index: 5
I (362) esp_psram: Found 8MB PSRAM device
I (366) esp_psram: Speed: 80MHz
I (370) cpu_start: Pro cpu up.
I (374) cpu_start: Starting app cpu, entry point is 0x4037551c
0x4037551c: call_start_cpu1 at /Users/Shared/B/SDK/esp/esp-idf/components/esp_system/port/cpu_start.c:154

I (0) cpu_start: App cpu up.
I (793) esp_psram: SPI SRAM memory test OK
I (802) cpu_start: Pro cpu start user code
I (802) cpu_start: cpu freq: 240000000 Hz
I (802) cpu_start: Application information:
I (805) cpu_start: Project name:     firmware
I (810) cpu_start: App version:      1.0.1-78-g30ed99b-dirty
I (817) cpu_start: Compile time:     Aug  7 2023 14:46:37
I (823) cpu_start: ELF file SHA256:  885204d567489924...
I (829) cpu_start: ESP-IDF:          v5.1-476-g3187b8b326
I (835) cpu_start: Min chip rev:     v0.0
I (840) cpu_start: Max chip rev:     v0.99
I (844) cpu_start: Chip rev:         v0.1
I (849) heap_init: Initializing. RAM available for dynamic allocation:
I (856) heap_init: At 3FC9A730 len 0004EFE0 (315 KiB): DRAM
I (863) heap_init: At 3FCE9710 len 00005724 (21 KiB): STACK/DRAM
I (869) heap_init: At 600FE010 len 00001FD8 (7 KiB): RTCRAM
I (876) esp_psram: Adding pool of 8192K of PSRAM memory to heap allocator
I (883) spi_flash: detected chip: gd
I (887) spi_flash: flash io: qio
W (891) spi_flash: Detected size(16384k) larger than the size in the binary image header(4096k). Using the size in the binary image header.
I (904) sleep: Configure to isolate all GPIO pins in sleep state
I (911) sleep: Enable automatic switching of GPIO sleep configuration
I (918) app_start: Starting scheduler on CPU0
I (923) app_start: Starting scheduler on CPU1
I (923) main_task: Started on CPU0
I (933) main_task: Calling app_main()
Heap summary for capabilities 0x00000800:
  At 0x3fc9a730 len 323552 free 303964 allocated 17640 min_free 303964
    largest_free_block 303104 alloc_blocks 44 free_blocks 1 total_blocks 45
  At 0x3fce9710 len 22308 free 21572 allocated 0 min_free 21572
    largest_free_block 21504 alloc_blocks 0 free_blocks 1 total_blocks 1
  At 0x600fe010 len 8152 free 7772 allocated 0 min_free 7772
    largest_free_block 7680 alloc_blocks 0 free_blocks 1 total_blocks 1
  Totals:
    free 333308 allocated 17640 min_free 333308 largest_free_block 303104
Heap summary for capabilities 0x00000400:
  At 0x3c110000 len 8388608 free 8386308 allocated 0 min_free 8386308
    largest_free_block 8257536 alloc_blocks 0 free_blocks 1 total_blocks 1
  Totals:
    free 8386308 allocated 0 min_free 8386308 largest_free_block 8257536
I (1009) gpio: GPIO[45]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (1018) gpio: GPIO[46]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (1027) epdiy_s3: using resolution 256x760
I (1032) epdiy_s3: num dma nodes: 1
I (1036) epdiy_s3: size: 1028 max: 4095
I (1041) epdiy_s3: pclk freq: 23000000 Hz
I (1045) epdiy_s3: line width: 12us, 276 cylces
I (1051) epdiy_s3: LCD init done.
E (1055) epd: lut size: 1024
I (1058) epdiy: thread id: 0
I (1062) epdiy: thread id: 1
Dimensions after rotation, width: 1024 height: 758

PG is up
current temperature: 20
PG is up
I (2033) epdiy: calculating diff..
I (2167) epdiy: highlevel diff area: x: 15, y: 15, w: 645, h: 315
I (2167) epdiy: starting update, phases: 30
W (2168) ####: area.width: 1024, area.x: 0, ctx->error: 2, EPD_WIDTH: 1024

assert failed: lcd_feed_frame render_lcd.c:152 (area.width == EPD_WIDTH && area.x == 0 && !ctx->error)

Backtrace: 0x40375b7a:0x3fcb3ee0 0x4037c911:0x3fcb3f00 0x40382315:0x3fcb3f20 0x40377a74:0x3fcb4040 0x403777b2:0x3fcb4490
0x40375b7a: panic_abort at /Users/Shared/B/SDK/esp/esp-idf/components/esp_system/panic.c:452

0x4037c911: esp_system_abort at /Users/Shared/B/SDK/esp/esp-idf/components/esp_system/port/esp_system_chip.c:84

0x40382315: __assert_func at /Users/Shared/B/SDK/esp/esp-idf/components/newlib/assert.c:81

0x40377a74: lcd_feed_frame at /Users/lanistor/C/hardware/epdiy/src/epd_driver/render_lcd.c:152 (discriminator 9)

0x403777b2: feed_display at /Users/lanistor/C/hardware/epdiy/src/epd_driver/render.c:251 (discriminator 1)

ELF file SHA256: 885204d567489924

Rebooting...
ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x3 (RTC_SW_SYS_RST),boot:0x9 (SPI_FAST_FLASH_BOOT)
Saved PC:0x420127c3
0x420127c3: __sfvwrite_r at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin12/xtensa-esp32s3-elf/src/newlib/newlib/libc/stdio/fvwrite.c:221

SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce3818,len:0x187c
load:0x403c9700,len:0x4
load:0x403c9704,len:0xda4
load:0x403cc700,len:0x3130
entry 0x403c9934
martinberlin commented 1 year ago

This you need to check how to solve I ask the same up there. Stay tuned and do your own research, try to understand what vroland did to make this work in S3. Please collaborate and try to help us expand the WiKi with your tests. Try a 16 bit display also in the 40 FPC connector.

vroland commented 1 year ago

Hi @martinberlin , Sorry, the v7 driver is unfortunately still in a rough state, I hope to be able to clean it up a bit next week. You're right about the includes, my plan is to conditionally compile the render method based on the chip used, but make the display config dynamic. You get the queue error if the line / waveform computation can't keep up with sending data to the LCD. This will be reworked into a nicer error hopefully. But at the speed you have it set to, It's likely a problem with either SPIRAM bandwidth (as @lanistor figured out) or CPU core frequency.

About that last assertion: Currently, the S3 driver code always draws full frames and doesn't skip empty lines. I'm wondering why you hit that assertion though, I think there is

  diff_area.x = 0;
  diff_area.y = 0;
  diff_area.width = EPD_WIDTH;
  diff_area.height = EPD_HEIGHT;

in highlevel.c in the s3 branch... Also, not all buffer modes are supported right now, e.g., 2PPB packing and monochrome mode. So examples that only use the highlevel API should work, but the ones that use 4bit-per-pixel buffers don't right now. As I said, the driver is still work in progress. Sorry about that, there is such much else going on and the driver work needs a block of focus time, it's not something I can just work on effectively for 30mins inbetween other things :/

martinberlin commented 1 year ago

@lanistor could you try the example/dragon. It is working for me correctly with a V7 board. Check latest updates in s3_lcd there is a way to set board and display dynamically now.

martinberlin commented 1 year ago

Thanks @vroland . Question:

Every time I use epdiy as an idf component in a project I face the challenge of adding manually a CMakeFiles. Could we add an additional one like this in the root of the project so it's easier for everybody:

set(basedir "src/epdiy")
set(app_sources "${basedir}/epdiy.c"
                "${basedir}/render.c"
                "${basedir}/output_lcd/render_lcd.c"
                "${basedir}/output_lcd/lcd_driver.c"
                "${basedir}/output_i2s/render_i2s.c"
                "${basedir}/output_i2s/rmt_pulse.c"
                "${basedir}/output_i2s/i2s_data_bus.c"
                "${basedir}/output_common/lut.c"
                "${basedir}/output_common/line_queue.c"
                "${basedir}/output_common/render_context.c"
                "${basedir}/font.c"
                "${basedir}/displays.c"
                "${basedir}/board_specific.c"
                "${basedir}/builtin_waveforms.c"
                "${basedir}/highlevel.c"
                "${basedir}/board/tps65185.c"
                "${basedir}/board/pca9555.c"
                "${basedir}/board/epd_board.c"
                "${basedir}/board/epd_board_common.c"
                "${basedir}/board/epd_board_lilygo_t5_47.c"
                "${basedir}/board/epd_board_v2_v3.c"
                "${basedir}/board/epd_board_v4.c"
                "${basedir}/board/epd_board_v5.c"
                "${basedir}/board/epd_board_v6.c"
                "${basedir}/board/epd_board_v7.c"
)

# Can also use IDF_VER for the full esp-idf version string but that is harder to parse. i.e. v4.1.1, v5.0-beta1, etc
if (${IDF_VERSION_MAJOR} GREATER 4)
    idf_component_register(SRCS ${app_sources} INCLUDE_DIRS "${basedir}/include" REQUIRES driver esp_timer esp_adc esp_lcd)
else()
    idf_component_register(SRCS ${app_sources} INCLUDE_DIRS "${basedir}/include" REQUIRES esp_adc_cal esp_timer)
endif()

# Does not seem to exist anymore lut.c in new version?
#set_source_files_properties("${basedir}/lut.c" PROPERTIES COMPILE_OPTIONS -mno-fix-esp32-psram-cache-issue)

Just a suggestion. Also this lut.c if I'm looking right does not exist anymore in latest version that is still not merged. This will make in my humble opinion this component much easier to add in future projects.

lanistor commented 1 year ago

@vroland Is EPD_DRAW_EMPTY_LINE_QUEUE an error? I got the below message while running latest code:

E (15961) demo: draw error: 400

Here is the whole message: 

I (27) boot: ESP-IDF v5.1.1-1-gd3c99ed3b8 2nd stage bootloader
I (27) boot: compile time Aug 25 2023 15:27:11
I (27) boot: Multicore bootloader
I (31) boot: chip revision: v0.1
I (35) boot.esp32s3: Boot SPI Speed : 80MHz
I (40) boot.esp32s3: SPI Mode       : DIO
I (45) boot.esp32s3: SPI Flash Size : 16MB
I (49) boot: Enabling RNG early entropy source...
I (55) boot: Partition Table:
I (58) boot: ## Label            Usage          Type ST Offset   Length
I (66) boot:  0 nvs              WiFi data        01 02 00011000 0000e000
I (73) boot:  1 phy_init         RF data          01 01 0001f000 00001000
I (81) boot:  2 factory          factory app      00 00 00020000 00400000
I (88) boot: End of partition table
I (92) esp_image: segment 0: paddr=00020020 vaddr=3c030020 size=f6f30h (1011504) map
I (282) esp_image: segment 1: paddr=00116f58 vaddr=3fc96900 size=02dcch ( 11724) load
I (285) esp_image: segment 2: paddr=00119d2c vaddr=40374000 size=062ech ( 25324) load
I (294) esp_image: segment 3: paddr=00120020 vaddr=42000020 size=23f10h (147216) map
I (323) esp_image: segment 4: paddr=00143f38 vaddr=4037a2ec size=0c5ach ( 50604) load
I (334) esp_image: segment 5: paddr=001504ec vaddr=600fe000 size=00070h (   112) load
I (342) boot: Loaded app from partition at offset 0x20000
I (342) boot: Disabling RNG early entropy source...
I (354) cpu_start: Multicore app
I (355) octal_psram: vendor id    : 0x0d (AP)
I (355) octal_psram: dev id       : 0x02 (generation 3)
I (358) octal_psram: density      : 0x03 (64 Mbit)
I (364) octal_psram: good-die     : 0x01 (Pass)
I (369) octal_psram: Latency      : 0x01 (Fixed)
I (374) octal_psram: VCC          : 0x01 (3V)
I (379) octal_psram: SRF          : 0x01 (Fast Refresh)
I (385) octal_psram: BurstType    : 0x01 (Hybrid Wrap)
I (391) octal_psram: BurstLen     : 0x01 (32 Byte)
I (396) octal_psram: Readlatency  : 0x02 (10 cycles@Fixed)
I (403) octal_psram: DriveStrength: 0x00 (1/1)
I (408) MSPI Timing: PSRAM timing tuning index: 11
I (413) esp_psram: Found 8MB PSRAM device
I (418) esp_psram: Speed: 80MHz
I (422) cpu_start: Pro cpu up.
I (425) cpu_start: Starting app cpu, entry point is 0x4037573c
0x4037573c: call_start_cpu1 at /Users/Shared/B/SDK/esp/esp-idf/components/esp_system/port/cpu_start.c:154

I (0) cpu_start: App cpu up.
I (884) esp_psram: SPI SRAM memory test OK
I (893) cpu_start: Pro cpu start user code
I (893) cpu_start: cpu freq: 240000000 Hz
I (893) cpu_start: Application information:
I (896) cpu_start: Project name:     firmware
I (901) cpu_start: App version:      1.0.1-89-g9f3f19a-dirty
I (908) cpu_start: Compile time:     Aug 25 2023 15:27:38
I (914) cpu_start: ELF file SHA256:  d3231b7370a6d78d...
I (920) cpu_start: ESP-IDF:          v5.1.1-1-gd3c99ed3b8
I (926) cpu_start: Min chip rev:     v0.0
I (930) cpu_start: Max chip rev:     v0.99
I (935) cpu_start: Chip rev:         v0.1
I (940) heap_init: Initializing. RAM available for dynamic allocation:
I (947) heap_init: At 3FC9CC40 len 0004CAD0 (306 KiB): DRAM
I (953) heap_init: At 3FCE9710 len 00005724 (21 KiB): STACK/DRAM
I (960) heap_init: At 600FE070 len 00001F78 (7 KiB): RTCRAM
I (967) esp_psram: Adding pool of 8192K of PSRAM memory to heap allocator
I (975) spi_flash: detected chip: gd
I (978) spi_flash: flash io: dio
I (982) sleep: Configure to isolate all GPIO pins in sleep state
I (989) sleep: Enable automatic switching of GPIO sleep configuration
I (996) app_start: Starting scheduler on CPU0
I (1001) app_start: Starting scheduler on CPU1
I (1001) main_task: Started on CPU0
I (1011) main_task: Calling app_main()
Heap summary for capabilities 0x00000800:
  At 0x3fc9cc40 len 314064 free 293964 allocated 18152 min_free 293964
    largest_free_block 286720 alloc_blocks 44 free_blocks 1 total_blocks 45
  At 0x3fce9710 len 22308 free 21572 allocated 0 min_free 21572
    largest_free_block 21504 alloc_blocks 0 free_blocks 1 total_blocks 1
  At 0x600fe070 len 8056 free 7676 allocated 0 min_free 7676
    largest_free_block 7168 alloc_blocks 0 free_blocks 1 total_blocks 1
  Totals:
    free 323212 allocated 18152 min_free 323212 largest_free_block 286720
Heap summary for capabilities 0x00000400:
  At 0x3c130000 len 8388608 free 8386308 allocated 0 min_free 8386308
    largest_free_block 8257536 alloc_blocks 0 free_blocks 1 total_blocks 1
  Totals:
    free 8386308 allocated 0 min_free 8386308 largest_free_block 8257536
I (1091) gpio: GPIO[45]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (1101) gpio: GPIO[46]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (1101) epdiy: using resolution 256x768
I (1111) epdiy: num dma nodes: 1
I (1111) epdiy: size: 1028 max: 4095
I (1121) epdiy: pclk freq: 20000000 Hz
I (1121) epdiy: line width: 14us, 280 cylces
I (1131) epdiy: LCD init done.
E (1131) epd: lut size: 65536
Dimensions after rotation, width: 1024 height: 768

PG is up
current temperature: 20
PG is up
I (3071) epdiy: calculating diff..
I (3261) epdiy: highlevel diff area: x: 15, y: 15, w: 645, h: 320
I (3271) epdiy: starting update, phases: 30
actual draw took 354ms.
PG is up
I (4741) epdiy: calculating diff..
I (4741) epdiy: highlevel diff area: x: 312, y: 384, w: 400, h: 20
I (4741) epdiy: starting update, phases: 4
actual draw took 50ms.
PG is up
I (5921) epdiy: calculating diff..
I (5921) epdiy: highlevel diff area: x: 317, y: 389, w: 39, h: 10
I (5921) epdiy: starting update, phases: 4
actual draw took 50ms.
PG is up
I (7091) epdiy: calculating diff..
I (7091) epdiy: highlevel diff area: x: 356, y: 389, w: 39, h: 10
I (7091) epdiy: starting update, phases: 4
actual draw took 50ms.
PG is up
I (8261) epdiy: calculating diff..
I (8261) epdiy: highlevel diff area: x: 395, y: 389, w: 39, h: 10
I (8261) epdiy: starting update, phases: 4
actual draw took 51ms.
PG is up
I (9431) epdiy: calculating diff..
I (9431) epdiy: highlevel diff area: x: 434, y: 389, w: 39, h: 10
I (9431) epdiy: starting update, phases: 4
actual draw took 50ms.
PG is up
I (10601) epdiy: calculating diff..
I (10601) epdiy: highlevel diff area: x: 473, y: 389, w: 39, h: 10
I (10601) epdiy: starting update, phases: 4
actual draw took 50ms.
PG is up
I (11781) epdiy: calculating diff..
I (11971) epdiy: highlevel diff area: x: 286, y: 451, w: 461, h: 84
I (11981) epdiy: starting update, phases: 30
actual draw took 346ms.
PG is up
I (12441) epdiy: calculating diff..
I (12451) epdiy: highlevel diff area: x: 712, y: 404, w: 0, h: 0
PG is up
I (12561) epdiy: calculating diff..
I (12571) epdiy: highlevel diff area: x: 473, y: 389, w: 39, h: 10
I (12571) epdiy: starting update, phases: 4
actual draw took 50ms.
PG is up
I (12741) epdiy: calculating diff..
I (12741) epdiy: highlevel diff area: x: 434, y: 389, w: 39, h: 10
I (12741) epdiy: starting update, phases: 4
actual draw took 50ms.
PG is up
I (12911) epdiy: calculating diff..
I (12921) epdiy: highlevel diff area: x: 395, y: 389, w: 39, h: 10
I (12921) epdiy: starting update, phases: 4
actual draw took 49ms.
PG is up
I (13091) epdiy: calculating diff..
I (13091) epdiy: highlevel diff area: x: 356, y: 389, w: 39, h: 10
I (13091) epdiy: starting update, phases: 4
actual draw took 49ms.
PG is up
I (13271) epdiy: calculating diff..
I (13271) epdiy: highlevel diff area: x: 317, y: 389, w: 39, h: 10
I (13271) epdiy: starting update, phases: 4
actual draw took 49ms.
PG is up
I (13511) epdiy: calculating diff..
I (13711) epdiy: highlevel diff area: x: 219, y: 484, w: 591, h: 109
I (13711) epdiy: starting update, phases: 30
actual draw took 346ms.
PG is up
I (15241) epdiy: calculating diff..
I (15441) epdiy: highlevel diff area: x: 15, y: 15, w: 795, h: 753
I (15441) epdiy: starting update, phases: 30
W (15461) epd_lcd: draw frame draw initiated, but an error flag is set: 400
W (15461) epd_lcd: draw frame draw initiated, but an error flag is set: 400
W (15471) epd_lcd: draw frame draw initiated, but an error flag is set: 400
......
W (15871) epd_lcd: draw frame draw initiated, but an error flag is set: 400
W (15871) epd_lcd: draw frame draw initiated, but an error flag is set: 400
actual draw took 446ms.
E (15961) demo: draw error: 400
PG is up
I (21141) epdiy: calculating diff..
I (21341) epdiy: highlevel diff area: x: 266, y: 25, w: 492, h: 743
I (21341) epdiy: starting update, phases: 30
W (21351) epd_lcd: draw frame draw initiated, but an error flag is set: 400
W (21351) epd_lcd: draw frame draw initiated, but an error flag is set: 400
W (21361) epd_lcd: draw frame draw initiated, but an error flag is set: 400
W (21361) epd_lcd: draw frame draw initiated, but an error flag is set: 400
W (213
martinberlin commented 1 year ago

Just put a lower bus_speed in display.c this is because at that speed the LCD cannot cope with the sending so fast. On 097OC4 at 8 bit I use 15 MHz, while with others can work faster, like 097TC2 was tested by Valentin at 22 MHz.

lanistor commented 1 year ago

Just put a lower bus_speed in display.c this is because at that speed the LCD cannot cope with the sending so fast. On 097OC4 at 8 bit I use 15 MHz, while with others can work faster, like 097TC2 was tested by Valentin at 22 MHz.

This works 👍.

But the rendering clarity or rendering speed, seems not so good as v5 board.

martinberlin commented 1 year ago

But the rendering clarity or rendering speed, seems not so good as v5 board.

I do not agree with this. Both the speed and rendering quality seem good to me. If you would like to contribute please read to the detail the LCD module It's easy to complain about something without giving any facts like measured statistics or video proof of what you experiment. This is also open source and everyone using it should realize that is a collective effort to make it happen. Closing here: There is a double Issue with S3 let's please keep this discussion at #203

lanistor commented 1 year ago

But the rendering clarity or rendering speed, seems not so good as v5 board.

I do not agree with this. Both the speed and rendering quality seem good to me. If you would like to contribute please read to the detail the LCD module It's easy to complain about something without giving any facts like measured statistics or video proof of what you experiment. This is also open source and everyone using it should realize that is a collective effort to make it happen. Closing here: There is a double Issue with S3 let's please keep this discussion at #203

Here is a video of the demo code running on v7 board, we can sees the behavior clearly, and the screen resolution is 1024 * 758: https://github.com/lanistor/assets/blob/master/epaper/v7/v7-board-demo.mov

martinberlin commented 1 year ago

This is looking fine for me. Make a video of this and a V5 board side-by-side and post it on #203 please so we take a look. I'm trying to keep only one issue open about one topic otherwise is hard to track.

At the time of closing this the initial request proposed my Mcer is done and hardware is ready to be tested in branch: s3_lcd

lanistor commented 1 year ago

Here is a video of the demo code running on v7 board, we can sees the behavior clearly, and the screen resolution is 1024 * 758:

I had uploaded two videos of behavior of v7 and v6 board: #203

lanistor commented 10 months ago

@martinberlin @vroland Hi, i cannot run the s3 board with the newest code on branhc s3_lcd, it will crash on start part, here is the log: I'm using ESP-IDF 5.2, and the s3 board created at 2023-07-25. I cannot find out the cause of this problem.

I (31) boot: ESP-IDF v5.2-beta1-263-ge49823f10c 2nd stage bootloader
I (31) boot: compile time Jan 11 2024 23:49:41
I (32) boot: Multicore bootloader
I (36) boot: chip revision: v0.1
I (40) qio_mode: Enabling default flash chip QIO
I (45) boot.esp32s3: Boot SPI Speed : 80MHz
I (50) boot.esp32s3: SPI Mode       : QIO
I (55) boot.esp32s3: SPI Flash Size : 2MB
I (59) boot: Enabling RNG early entropy source...
I (65) boot: Partition Table:
I (68) boot: ## Label            Usage          Type ST Offset   Length
I (76) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (83) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (91) boot:  2 factory          factory app      00 00 00010000 00177000
I (98) boot: End of partition table
I (102) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=d4f98h (872344) map
I (243) esp_image: segment 1: paddr=000e4fc0 vaddr=3fc95000 size=02510h (  9488) load
I (245) esp_image: segment 2: paddr=000e74d8 vaddr=40374000 size=08b40h ( 35648) load
I (255) esp_image: segment 3: paddr=000f0020 vaddr=42000020 size=1f9a0h (129440) map
I (277) esp_image: segment 4: paddr=0010f9c8 vaddr=4037cb40 size=08428h ( 33832) load
I (284) esp_image: segment 5: paddr=00117df8 vaddr=600fe000 size=00064h (   100) load
I (291) boot: Loaded app from partition at offset 0x10000
I (291) boot: Disabling RNG early entropy source...
I (305) cpu_start: Multicore app
I (306) octal_psram: vendor id    : 0x0d (AP)
I (306) octal_psram: dev id       : 0x02 (generation 3)
I (309) octal_psram: density      : 0x03 (64 Mbit)
I (315) octal_psram: good-die     : 0x01 (Pass)
I (320) octal_psram: Latency      : 0x01 (Fixed)
I (325) octal_psram: VCC          : 0x01 (3V)
I (330) octal_psram: SRF          : 0x01 (Fast Refresh)
I (336) octal_psram: BurstType    : 0x01 (Hybrid Wrap)
I (342) octal_psram: BurstLen     : 0x01 (32 Byte)
I (347) octal_psram: Readlatency  : 0x02 (10 cycles@Fixed)
I (353) octal_psram: DriveStrength: 0x00 (1/1)
I (359) MSPI Timing: PSRAM timing tuning index: 5
I (364) esp_psram: Found 8MB PSRAM device
I (369) esp_psram: Speed: 80MHz
I (663) esp_psram: SPI SRAM memory test OK
I (671) cpu_start: Pro cpu start user code
I (672) cpu_start: cpu freq: 240000000 Hz
I (672) cpu_start: Application information:
I (675) cpu_start: Project name:     firmware
I (680) cpu_start: App version:      1.0.2-83-g7648436-dirty
I (686) cpu_start: Compile time:     Jan 11 2024 23:50:41
I (692) cpu_start: ELF file SHA256:  04d0d137a9e1db2d...
Warning: checksum mismatch between flashed and built applications. Checksum of built application is 5610163eb998d00e566fcba757e4b5487dcc4c125f027971ecf342d3bb33fdca
I (698) cpu_start: ESP-IDF:          v5.2-beta1-263-ge49823f10c
I (705) cpu_start: Min chip rev:     v0.0
I (709) cpu_start: Max chip rev:     v0.99
I (714) cpu_start: Chip rev:         v0.1
I (719) heap_init: Initializing. RAM available for dynamic allocation:
I (726) heap_init: At 3FC98040 len 000516D0 (325 KiB): RAM
I (732) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM
I (738) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
I (744) heap_init: At 600FE064 len 00001F84 (7 KiB): RTCRAM
I (751) esp_psram: Adding pool of 8192K of PSRAM memory to heap allocator
I (759) spi_flash: detected chip: gd
I (762) spi_flash: flash io: qio
W (766) spi_flash: Detected size(16384k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
W (780) i2c: This driver is an old driver, please migrate your application code to adapt `driver/i2c_master.h`
I (790) sleep: Configure to isolate all GPIO pins in sleep state
I (797) sleep: Enable automatic switching of GPIO sleep configuration
I (804) main_task: Started on CPU0
I (814) esp_psram: Reserving pool of 32K of internal memory for DMA/internal allocations
I (814) main_task: Calling app_main()
I (824) gpio: GPIO[45]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (834) gpio: GPIO[46]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (844) epdiy: using resolution 200x600
I (844) epdiy: num dma nodes: 1
I (844) epdiy: size: 804 max: 4095
I (854) epdiy: pclk freq: 20000000 Hz
I (854) epdiy: line width: 11us, 220 cylces
I (864) epdiy: LCD init done.
E (864) epd: lut size: 65536

assert failed: 0x4037f063
0x4037f063: prvInitialiseNewTask at /Users/Shared/SDK/esp5/esp-idf/components/freertos/FreeRTOS-Kernel/tasks.c:1061 (discriminator 1)

Backtrace: 0x4037572a:0x3fc9bb60 0x4037db49:0x3fc9bb80 0x403832e5:0x3fc9bba0 0x4037f063:0x3fc9bbe0 0x4038046a:0x3fc9bc10 0x42007d09:0x3fc9bc50 0x420079e9:0x3fc9bc90 0x42007157:0x3fc9bcb0 0x42007547:0x3fc9bcf0 0x4201edc7:0x3fc9bd10
0x4037572a: panic_abort at /Users/Shared/SDK/esp5/esp-idf/components/esp_system/panic.c:472

0x4037db49: esp_system_abort at /Users/Shared/SDK/esp5/esp-idf/components/esp_system/port/esp_system_chip.c:93

0x403832e5: __assert_func at /Users/Shared/SDK/esp5/esp-idf/components/newlib/assert.c:40

0x4037f063: prvInitialiseNewTask at /Users/Shared/SDK/esp5/esp-idf/components/freertos/FreeRTOS-Kernel/tasks.c:1061 (discriminator 1)

0x4038046a: xTaskCreatePinnedToCore at /Users/Shared/SDK/esp5/esp-idf/components/freertos/esp_additions/freertos_tasks_c_additions.h:284

0x42007d09: epd_renderer_init at /Users/lanistor/C/hardware/epdiy/src/render.c:265

0x420079e9: epd_init at /Users/lanistor/C/hardware/epdiy/src/epdiy.c:491

0x42007157: idf_setup at /Users/lanistor/C/hardware/epdiy/examples/demo/main/main.c:41

0x42007547: app_main at /Users/lanistor/C/hardware/epdiy/examples/demo/main/main.c:256

0x4201edc7: main_task at /Users/Shared/SDK/esp5/esp-idf/components/freertos/app_startup.c:208
martinberlin commented 10 months ago

Please use main branch. I still use 5.1 but I will update and if I can reproduce it will open this issue again or even better make a new one with the error detail since it’s easier to reproduce

martinberlin commented 10 months ago

As an additional comment @lanistor Latest official “non beta” release is 5.1.2 If you use a beta release you will likely have to face beta errors which are really not meant to be fixed here. Please use a stable release.

Also if I see that correctly the only new chip that adds 5.2 is H4 so you are not having any benefit using this version right now

lanistor commented 10 months ago

As an additional comment @lanistor Latest official “non beta” release is 5.1.2 If you use a beta release you will likely have to face beta errors which are really not meant to be fixed here. Please use a stable release.

Also if I see that correctly the only new chip that adds 5.2 is H4 so you are not having any benefit using this version right now

Thanks, i changed to release/v5.1, and the problem disappeared.