About HLS ERROR: [IMPL 213-28] solution

[XS30]

Hi,

"ERROR: [IMPL 213-28] Failed to generate IP. command ‘ap_source’ returned error code"

This error occurs when using HLS to synthesize “Example2: lstm autoencoder targeting anomaly detection”. It can be solved by modifying the system time to 2021. Maybe you can write the solution into readme.

Thank you for your demo and wish you a happy New Year！

[walkieq]

Many thanks for pointing out. From your description it looks like an FPGA tool license issue ?

I will leave this issue open so that if anyone meets the same issue they can know the workaround.

[PtL19]

Why I have the same problem while I am using 'Vitis HLS 2022.1'...? And I got the 'y2k22_patch-1.2.zip', but it is not for release 2022.1, sadly.

[walkieq]

Xilinx have provided a patch for their Vivado tools to solve this issue of IP export.

"Export IP Invalid Argument / Revision Number Overflow Issue (Y2K22)" https://support.xilinx.com/s/article/76960?language=en_US

[walkieq]

Why I have the same problem while I am using 'Vitis HLS 2022.1'...? And I got the 'y2k22_patch-1.2.zip', but it is not for release 2022.1, sadly.

Could you paste more log information for this error? The y2k22_patch should work for the Vivados up to 2021.02.

[PtL19]

Why I have the same problem while I am using 'Vitis HLS 2022.1'...? And I got the 'y2k22_patch-1.2.zip', but it is not for release 2022.1, sadly.

Could you paste more log information for this error? The y2k22_patch should work for the Vivados up to 2021.02.

ERROR: [IMPL 213-28] Failed to generate IP.

command 'ap_source' returned error code

while executing

"source E:/Pt.L/LiuQL/FPGAcodes/fdefl/solution1/export.tcl"

invoked from within

"hls::main E:/Pt.L/LiuQL/FPGAcodes/fdefl/solution1/export.tcl"

("uplevel" body line 1)

invoked from within

"uplevel 1 hls::main {*}$args"

(procedure "hls_proc" line 5)

invoked from within

"hls_proc $argv" fdefl:solution1 2022年6月23日 下午3:43:47

[PtL19]

Why I have the same problem while I am using 'Vitis HLS 2022.1'...? And I got the 'y2k22_patch-1.2.zip', but it is not for release 2022.1, sadly.

Could you paste more log information for this error? The y2k22_patch should work for the Vivados up to 2021.02.

I thought it is the same problem as above. And I thought this patch would work for Vitis HLS 2022.1 too. But it did not even installed successfully. 'README' also says this patch is not for 2022.1

[walkieq]

Why I have the same problem while I am using 'Vitis HLS 2022.1'...? And I got the 'y2k22_patch-1.2.zip', but it is not for release 2022.1, sadly.

Could you paste more log information for this error? The y2k22_patch should work for the Vivados up to 2021.02.

I thought it is the same problem as above. And I thought this patch would work for Vitis HLS 2022.1 too. But it did not even installed successfully. 'README' also says this patch is not for 2022.1

Yes. It looks like the same issue and should be solved by Xilinx.
Besides, because our codes are based on the HLS4ML library which is only compatiable to Vivado HLS up to 2020.01, Vitis HLS 2022 may not work on this repository.

[PtL19]

Why I have the same problem while I am using 'Vitis HLS 2022.1'...? And I got the 'y2k22_patch-1.2.zip', but it is not for release 2022.1, sadly.

Could you paste more log information for this error? The y2k22_patch should work for the Vivados up to 2021.02.

I thought it is the same problem as above. And I thought this patch would work for Vitis HLS 2022.1 too. But it did not even installed successfully. 'README' also says this patch is not for 2022.1

Yes. It looks like the same issue and should be solved by Xilinx. Besides, because our codes are based on the HLS4ML library which is only compatiable to Vivado HLS up to 2020.01, Vitis HLS 2022 may not work on this repository.

Thanks, I will use 2020.1 for now, and wait for Xilinx's patch.