[x] On the BMS side there are only 2 GND pins (ran out ☹) and one of them would go to a wired power supply and it seems on the main side it’s 6 pins. So only 1 of the gnd pins will go to the BMS and im not sure if you have a plan with the other 5 gnd pins
[I was using your same set up you showed me earlier in the term, i didn' know you chnaged it. I'll take a look at the updated one]
[x] Not a complaint but I double checked all the molex mini-fit jr connectors could use the same crimp tool/same style of crimps and we should be good
[x] On IC1 you’re missing the pull-up resistors on the 4 i2c encoder lines. See datasheet page 16
[Pull ups are on encoder boards]
[x] Error pin of IC4 is disconnected, are there any plans to use it?
[No plans to use it]
[x] IC4 shdn pin is hard connected to 5V, im assuming we’re always going to have the regulator enabled?
[Yea was thinking of having it always connected] - what are your thoughts?
[x] Add a net label to vsense
Layout review:
[x] Missing thermal relief on gnd pads and pins, might be difficult to solder these joints
[ ] Double check design rule check, you have part outlines that are off-board. Was this intended?
[x] Mid layers can have their copper weight increased from 0.5oz to 1oz
JLC only has 0.5oz for inner layers
[x] IC4 the power traces (5V and 3V3) can be increased for better heat dissipation (like to 2.5mm?)
[x] Not sure how much current IC1 will actually draw but they suggest adding more vias to VCC and GND
[It seems like it wont be more than a couple mA. Won't be adding more]
[x] I would route IBAT away from the I2C lines, the SCL rising and falling edges could mess with IBAT’s analog voltage value. Perhaps routing between pins 5 and 4 is an option instead?
[x] Board mounting holes shouldn’t be connected to GND. Chassis will only be connected to gnd from a single point and it’ll be on the BMS side
[x] Some trace widths are 0.2mm instead of the 0.254mm used elsewhere. For example, pin 9 on J17, pin 2 on J9, pins 6, 7, 8, 14, 15, 16 on J17 Is that on purpose? It's not a huge deal, 0.2mm is just starting to get a little small.
[x] The silkscreen for TP5 should be moved so it's not under D1.
[x] There's a step in the trace going to IC1, near the R3 silkscreen. I think there's enough clearance to straighten that out.
[x] The trace going to pin 4 on J12 should be routed closer to the center of the pin.
[x] Might be a good idea to increase the spoke width on the polygon pour 5V_L01_P043
[x] The air gap on polygon pour NETC6_1_L01_P044 should be increased
Coops-J
commented
2 years ago
Schematic Review:
Layout review: