What steps will reproduce the problem?
1. Compile the library for ARM CPU with optimization
2. Run a simple test that deserializes JSON document
3. The process will core due to SIGBUS signal resulted from misaligned data
access.
What is the expected output? What do you see instead?
The process should not produce SIGBUS signal and core file.
What version of the product are you using? On what operating system?
ARM CPU
Please provide any additional information below.
The cause of the misaligned data access was due to assumptions made in memory
pool class - it has no provisions for allocated memory chunk to be aligned on 4
byte boundary like malloc does in crt allocator rendering library useless if no
changes made to the library for architectures sensitive to data alignment (such
as ARM).
Original issue reported on code.google.com by okosen...@gmail.com on 6 Nov 2012 at 3:02
Original issue reported on code.google.com by
okosen...@gmail.com
on 6 Nov 2012 at 3:02