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iDEA FPGA Soft Processor
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Correct and complete instruction format doc #1

Closed rhinton closed 6 years ago

rhinton commented 8 years ago

It appears the published papers on iDEA use a different instruction format. In particular, the opcode has moved to the MSBs, and the conditions/flags to the LSBs. I am putting together a preliminary guess at the instruction format at the wiki page [[InstructionFormat]]. Please correct any mistakes and fill out missing information. Thanks!

hycheah commented 8 years ago

Hi, will check when I get back

On Thursday, 24 December 2015, Ryan Hinton notifications@github.com wrote:

It appears the published papers on iDEA use a different instruction format In particular, the opcode has moved to the MSBs, and the conditions/flags to the LSBs I am putting together a preliminary guess at the instruction format at the wiki page [[InstructionFormat]] Please correct any mistakes and fill out missing information Thanks!

— Reply to this email directly or view it on GitHub https://github.com/archntu/idea/issues/1.

rhinton commented 8 years ago

Great, thanks. I guess the real question is whether there is any detailed architecture information on the latest implementation here in git. For example, what are the opcodes? I've spent a little time toward creating an LLVM backend for iDEA, but it's too much work to guess from the source code.

I love the idea of a small, simple, fast (high MHz) processor. I have some suggestions for register forwarding (of a sort) and I/O. I agree that ideally the processor should be a thin wrapper around some BRAMs for instruction and data memory, LUT RAM for registers, and DSP48 for ALU and most everything else.

hycheah commented 8 years ago

The idea instruction set has undergone many changes since its first version. For compiler compatibility reasons, I adopted the MIPS I instructions set. You could find the reference from this link: http://opencores.org/project,plasma,opcodes

You can also find the list of supported instructions from the defines.v file in the rtl/ folder

On Sun, Dec 27, 2015 at 1:56 PM, Ryan Hinton notifications@github.com wrote:

Great, thanks. I guess the real question is whether there is any detailed architecture information on the latest implementation here in git. For example, what are the opcodes? I've spent a little time toward creating an LLVM backend for iDEA, but it's too much work to guess from the source code.

I love the idea of a small, simple, fast (high MHz) processor. I have some suggestions for register forwarding (of a sort) and I/O. I agree that ideally the processor should be a thin wrapper around some BRAMs for instruction and data memory, LUT RAM for registers, and DSP48 for ALU and most everything else.

— Reply to this email directly or view it on GitHub https://github.com/archntu/idea/issues/1#issuecomment-167383889.

rhinton commented 8 years ago

Do you have any numbers on the change (if any) in achievable frequency and size when switching to the MIPS instruction set? I like the idea of using a backend like LLVM to move as much of the complexity as possible into the compiler. In other words, minimize the in-logic muxing in the FPGA. Tailor the instruction layouts to the DSP48 inputs. Make the HDL as simple as possible. Make the machine as consistent as possible in the FPGA fabric, and make the compiler deal with the resulting idiosyncrasies.

Can you point me to an earlier commit that has the instruction set as described in your paper(s)? Does it make sense to branch from this point for my experiments?

Thanks!

The idea instruction set has undergone many changes since its first version. For compiler compatibility reasons, I adopted the MIPS I instructions set. You could find the reference from this link: http://opencores.org/project,plasma,opcodes

You can also find the list of supported instructions from the defines.v file in the rtl/ folder

On Sun, Dec 27, 2015 at 1:56 PM, Ryan Hinton notifications@github.com wrote:

Great, thanks. I guess the real question is whether there is any detailed architecture information on the latest implementation here in git. For example, what are the opcodes? I've spent a little time toward creating an LLVM backend for iDEA, but it's too much work to guess from the source code.

I love the idea of a small, simple, fast (high MHz) processor. I have some suggestions for register forwarding (of a sort) and I/O. I agree that ideally the processor should be a thin wrapper around some BRAMs for instruction and data memory, LUT RAM for registers, and DSP48 for ALU and most everything else.

— Reply to this email directly or view it on GitHub https://github.com/archntu/idea/issues/1#issuecomment-167383889.

Reply to this email directly or view it on GitHub: https://github.com/archntu/idea/issues/1#issuecomment-167922359

hycheah commented 8 years ago

You could checkout the first few commits if you want the earlier version of idea. The latest frequency is about ~480MHz

On Thu, Dec 31, 2015 at 10:46 AM, Ryan Hinton notifications@github.com wrote:

Do you have any numbers on the change (if any) in achievable frequency and size when switching to the MIPS instruction set? I like the idea of using a backend like LLVM to move as much of the complexity as possible into the compiler. In other words, minimize the in-logic muxing in the FPGA. Tailor the instruction layouts to the DSP48 inputs. Make the HDL as simple as possible. Make the machine as consistent as possible in the FPGA fabric, and make the compiler deal with the resulting idiosyncrasies.

Can you point me to an earlier commit that has the instruction set as described in your paper(s)? Does it make sense to branch from this point for my experiments?

Thanks!

  • Ryan

The idea instruction set has undergone many changes since its first version. For compiler compatibility reasons, I adopted the MIPS I instructions set. You could find the reference from this link: http://opencores.org/project,plasma,opcodes

You can also find the list of supported instructions from the defines.v file in the rtl/ folder

On Sun, Dec 27, 2015 at 1:56 PM, Ryan Hinton notifications@github.com wrote:

Great, thanks. I guess the real question is whether there is any detailed architecture information on the latest implementation here in git. For example, what are the opcodes? I've spent a little time toward creating an LLVM backend for iDEA, but it's too much work to guess from the source code.

I love the idea of a small, simple, fast (high MHz) processor. I have some suggestions for register forwarding (of a sort) and I/O. I agree that ideally the processor should be a thin wrapper around some BRAMs for instruction and data memory, LUT RAM for registers, and DSP48 for ALU and most everything else.

— Reply to this email directly or view it on GitHub https://github.com/archntu/idea/issues/1#issuecomment-167383889.

Reply to this email directly or view it on GitHub: https://github.com/archntu/idea/issues/1#issuecomment-167922359

— Reply to this email directly or view it on GitHub https://github.com/archntu/idea/issues/1#issuecomment-168112766.