Begin schematic mods for I2C.

[kevinkwan23]

This change is 

[AidanHa]

Schematics look fine to me. BTW who exactly is working on this board?

[zx100x100]

It has bounced around a bit, from now on Zachary is going to be the lead on it.

[ZTeper]

Should we have more meaningful silkscreen labels for the connectors? Names like J2, J3, etc. can be confusing. Meaningful silkscreen labels might be useful for people assembling/debugging the board.

[zx100x100]

J2, J3, ect are just the reference designators. Don't delete them, but it would be good to add silkscreen text for the connector pinout, as well as a channel number for each sensor connector.

[amihaila]

J2, J3, ect are just the reference designators. Don't delete them, but it would be good to add silkscreen text for the connector pinout, as well as a channel number for each sensor connector.

I personally usually hide the reference designator silkscreen, and replace it with a meaningful name.

[ZTeper]

The first version of routing is finished. Please leave comments on how to improve the routing and the board in general. Please also leave suggestions about where to put copper pour areas (copper zones), since there currently are none.

[ZTeper]

J2, J3, ect are just the reference designators. Don't delete them, but it would be good to add silkscreen text for the connector pinout, as well as a channel number for each sensor connector.

I personally usually hide the reference designator silkscreen, and replace it with a meaningful name.

[ZTeper]

Hello PCB review folks. Let me know about:

• Whether we should switch to a 4-layer design. If so, what sorts of signals would go on each of the 4 layers?
• How I can improve the placement/routing on the current design.

Thanks.

[QuantumManiac]

So, I looked through the entire project instead of just the PCB layout out of boredom. Just a few things I noticed:

• It seems that you are using a custom footprint named C_0805_HandSoldering for the capacitors. What's the difference between this and the C_0805_2012Metric_Pad1.15x1.40mm_HandSolder that comes in the KiCAD Capacitor_SMD library? Do the pads need to be larger?

• I'm not too familiar with this, but does the Instrumentation Amp need to have a KiCAD project file of its own? It's just a schematic, isn't it?

• I'm not that familiar with the standard for where to put custom footprints for projects, but should the custom footprints used be somewhere other than the main project directory? Perhaps in lib or a sub-folder in the project directory? @zx100x100, how's it usually done?

• It seems that there are a few footprint and symbol libraries floating around in your project-specific libraries that have absolute paths on Alex's computer. Since they're not causing any issues I'm guessing that they're not being used so you might want to get rid of them.

Okay, now that that's done with, Stuff related to PBC Layout/Design here

Layout and routing seems pretty good. Looks super cool in my opinion. Just a few things I noticed:

• Would it be possible to get rid of this fork in between J2 and J4 and just route all three traces directly from the pad?

• There's a few kinks near C6 and R4 that could probably be straightened out.

• Avoid right-angles when possible. I'm sure that most of these can be replaced with acute angles instead. This particular example is found near C2

• Some more right angles near the bottom-right of the board. The top-left one would be pretty tricky to re-route so you might be better off keeping that as is.

• More right-angles for SW1

• I noticed that you don't have a copper pour for the top of the board. Perhaps you could make one for power?

• There seems to be quite a bit of empty space on both the top and bottom of the board. It'll be difficult now that you've already done routing, but it might be nice to spread out the parts a bit more. Definitely would make it easier when soldering.

I just realized that I mentioned nothing about a 4-layer design. Unfortunately, I'm not too familiar with them so you'll probably want to wait for someone else to comment on them.

Observations, not review comments:

• There's a lot of useless cache, bak, and (potentially) rescue files in the project directory that shouldn't be pushed to the repo, which led me to realize that the .gitignore for the repo isn't configured to handle KiCAD stuff. Just something to point out, you don't really have to do anything about it. Someone should setup the .gitignore unless there's a reason as to why it's not.

• We should probably set up all the Waterloo Rocketry logo footprints to be in a folder in lib, like how it is in canhw, to make it easier for projects to use them.

I'll probably make Github issues for these.

[zx100x100]

Hello PCB review folks. Let me know about:

• Whether we should switch to a 4-layer design. If so, what sorts of signals would go on each of the 4 layers?
• How I can improve the placement/routing on the current design.

Thanks.

I Think it would be cool to make it a 4 layer board. The standard layer stack-up for a 4 layer board is as follows: Layer 1: Top signal layer Layer 2: GND Plane Layer 3: PWR Plane Layer 4: Bottom signal layer

Here is an EEV blog video comparing 2 and 4 layer boards: https://www.eevblog.com/2019/02/13/eevblog-1176-2-layer-vs-4-layer-pcb-emc-tested/

[ZTeper]

@zach Where is the "I2C valve" board? Can you please give an example of what you mean by switch numbering?

[ZTeper]

Should we add Test Points to the PCB? Like +12V, +10V, +5V, GND points?

[ZTeper]

Thanks Chamath. With respect to the SCL and SDA lines, I spaced them out deliberately to minimize cross-talk interference. Let me know if you think the spacing is unnecessary or if the lines should be closer together. Thanks for the helpful feedback :)

[QuantumManiac]

Thanks Chamath. With respect to the SCL and SDA lines, I spaced them out deliberately to minimize cross-talk interference. Let me know if you think the spacing is unnecessary or if the lines should be closer together. Thanks for the helpful feedback :)

Ah yes, that's a good point. In that case, I think that you can leave a decent gap between the two lines while still removing a lot of the bends. I'm not too familiar with how cross-talk would work between the SCL and SDA lines, but I'd imagine that a minimum clearance of ~40 mils, as found near the mounting hole, is acceptable. Maybe something similar to this might work better?

To be honest, it's probably not that big of a big deal. I'm just a sucker for clean looks and all that.

[lwbantoto]

Schematic Notes

• Use a PTC resettable fuse. Add the part number of the fuse in the schematic
• Ceramic capacitors are fine for LDOs. Make sure to specify the rated voltage of the caps on the schematic so we can see if they're properly derated.
• Add a test point for 12V and 10V.
• Make a note of how much expected current will be drawn from the LDO @ 10V

• Add fuses and a small decoupling capacitor (0.1uF) wherever power leaves the board

• Missing LED part number
• Missing I2C pullup resistors

• Add RC debounce circuit for switches. 10ms debounce time should be sufficient

• Add a fuse and decoupling capacitor where 10V leaves the board
• What value is R2? Why isn't it on the schematic?

General

• Add test points for important signals. Make sure to have sufficient ground test points as well

[zx100x100]

I agree with a many of these comments, although I do have thoughts on some of them:

The dip switches are steady state, never to be changed in operation as they select the I2C address, debouching is therefore unnecessary and is just more parts and more time to assemble.

R2 doesn't have a value as it is variable depending on the desired gain (note the text beside it that gives the gain equation)

F1 is supposed to already be a PTC, but yes, it should be noted as such, and the desired trip value should be added.

I2C pull ups will be added externally, you shouldn't add pull ups to every device on the bus.

I don't mind the LED not having a part number, there is no need to specify, any 1206 part is fine.

bypass caps on the output isn't a bad idea, although these connect to a few meters of cabling, I doubt the bypass caps would do much more than what the bulk bypass cap is already doing.

Fuses seem unnecessary on every output and would add extra cost and assembly labor, not to mention another part to debug.

[zx100x100]

Please add I2C to the name, or make it clear this board is different from regular pancake in some way.

[QuantumManiac]

Looking good! Just a few random things to point out while I was taking a look at the project libraries:

It seems that there's some project-specific symbol library that is pathed to Alex's computer. I don't think it's causing issues but do get rid of it.

Same with these project-specific footprint libraries

Other than that, take care of the reviews from the others and do a bit more route tidying. Looks very close to completion!

[jacobdeery]

Can you please remove the space in the filepath (I2C Pancake --> I2C_Pancake or something similar)?

[AidanHa]

Seems like my schematic liubrary didn't load properly as well. Board looks good to me once the above comments just addressed ^^

[AidanHa]

change requested, but I assume its outdated. I'm down to merge

[ZTeper]

Approved. Let's merge.

[ZTeper]

@JaredWatson can we dismiss your old requested change?

[jacobdeery]

which one of y'all wants to actually hit the merge button?