Improve under-aligned buffers for AltiVec and Power8

[noloader]

Intel and ARM processors are tolerant of under-aligned buffers when using crypto instructions. AltiVec and Power8 are less tolerant, and they simply ignore the three low-order bits to ensure an address is aligned. The AltiVec and Power8 have caused a fair number of wild writes on the stack and in the heap.

We cannot enable the AltiVec and Power8 in-core crypto until the addresses are properly aligned for the CPUs.

This ticket will track changes related to buffer alignments for messages that are handled on AltiVec and Power8 data paths.

[noloader]

Power8 AES encryption was cut-in at Commit 7fb34e9b0894.

We picked some low-hanging fruit when it came to under-aligned buffers. However, most of them remained in place. Instead, we switched to VSX unaligned loads. We pay a small performance penalty, but it "just works" for users.

Closing ticket.