I realize that EEPROM address space is actually flash (PROGMEM in a sense), but what are the first and last addresses? (Examples: 0x0 and 0x199, or sizeof(SOME_SKETCHNAME) and sizeof(PGMSPACE) - sizeof(SOME_SKETCHNAME)....)
Am I correct in seeing that the beginning address (0x0) always is the same flash cell even though a new and different-size sketch may get uploaded into the board? This indicates that sketches are loaded into the highest flash addresses possible, and EEPROM is always the lowest addresses.
Or is it that a constant-sized area of flash is reserved for EEPROM and never allowed to hold any sketch?
Thank you!
UPDATE: I learned from the data sheet that one of several discrete configurations are available whereby zero to eight blocks of flash, 1K each in size, are dedicated for EEPROM. My IDE compile-time STDOUT indicates my compiling defaults are for one 1K block dedicated for EEPROM, leaving me 32K less 2K for sketch flash storage (each block used for EEPROM comes at a cost of twice that much taken from sketch flash). That default setting is exactly what I need, but that flash cost doubling leaves my sketch size disappointingly too large. I'll downsize it somehow....
For the WEMOS XI:
I realize that EEPROM address space is actually flash (PROGMEM in a sense), but what are the first and last addresses? (Examples: 0x0 and 0x199, or sizeof(SOME_SKETCHNAME) and sizeof(PGMSPACE) - sizeof(SOME_SKETCHNAME)....)
Am I correct in seeing that the beginning address (0x0) always is the same flash cell even though a new and different-size sketch may get uploaded into the board? This indicates that sketches are loaded into the highest flash addresses possible, and EEPROM is always the lowest addresses.
Or is it that a constant-sized area of flash is reserved for EEPROM and never allowed to hold any sketch?
Thank you!
UPDATE: I learned from the data sheet that one of several discrete configurations are available whereby zero to eight blocks of flash, 1K each in size, are dedicated for EEPROM. My IDE compile-time STDOUT indicates my compiling defaults are for one 1K block dedicated for EEPROM, leaving me 32K less 2K for sketch flash storage (each block used for EEPROM comes at a cost of twice that much taken from sketch flash). That default setting is exactly what I need, but that flash cost doubling leaves my sketch size disappointingly too large. I'll downsize it somehow....