some problems which I find

[xxwjcode]

Hello，I am a student. When I used it to test my use cases, the results were not consistent with my expectations. the problem of my testcase is

13923 0 00000000800002c8 800000b7 r 0000000000000001 ffffffff80000000 lui x1, -0x80000

13924 0 00000000800002cc 8000bf13 r 000000000000001e 0000000000000000 sltiu x30, x1, 0x800

The value of reg x1 is 0xffffffff80000000, and the value of imm is 0x800. the imm should extend to 64-bits with sign, so the result should be 1,but the test is 0.

And I found lots of similar mistake cased of extending to 64-bits with sign.

I try to change the code of Hart.cpp. I changed the function of “”“ template void Hart::execSltiu(const DecodedInst di) { URV imm = di->op2(); URV v = intRegs.read(di->op1()) < imm ? 1 : 0; intRegs.write(di->op0(), v); } “”” to “”” template void Hart::execSltiu(const DecodedInst di) { //URV imm = di->op2(); URV imm = SRV(int32t(di->op2())); // Sign extend to 64-bits URV v = intRegs.read(di->op1()) < imm ? 1 : 0; intRegs_.write(di->op0(), v); } “”” then ,I tested it .the problem is solved.

[jrahmeh]

Thank you. I will fix the code accordingly.

On Tue, Oct 8, 2019, 12:36 AM xxwjcode notifications@github.com wrote:

Hello，I am a student. When I used it to test my use cases, the results were not consistent with my expectations. the problem of my testcase is

13923 0 00000000800002c8 800000b7 r 0000000000000001 ffffffff80000000 lui

x1, -0x80000

13924 0 00000000800002cc 8000bf13 r 000000000000001e 0000000000000000

sltiu x30, x1, 0x800 The value of reg x1 is 0xffffffff80000000, and the value of imm is 0x800. the imm should extend to 64-bits with sign, so the result should be 1,but the test is 0.

And I found lots of similar mistake cased of extending to 64-bits with sign.

I try to change the code of Hart.cpp. I changed the function of “”“ template void Hart::execSltiu(const DecodedInst di) { URV imm = di->op2(); URV v = intRegs.read(di->op1()) < imm ? 1 : 0; intRegs.write(di->op0(), v); } “”” to “”” template void Hart::execSltiu(const DecodedInst di) { //URV imm = di->op2(); URV imm = SRV(int32t(di->op2())); // Sign extend to 64-bits URV v = intRegs.read(di->op1()) < imm ? 1 : 0; intRegs_.write(di->op0(), v); } “”” then ,I tested it .the problem is solved.

— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub https://github.com/westerndigitalcorporation/swerv-ISS/issues/15?email_source=notifications&email_token=AASHQX5BNUKU4DYJ45XXKOTQNQL65A5CNFSM4I6NFFE2YY3PNVWWK3TUL52HS4DFUVEXG43VMWVGG33NNVSW45C7NFSM4HQH6KCA, or mute the thread https://github.com/notifications/unsubscribe-auth/AASHQX6NSRTJCEK7BB7SYD3QNQL65ANCNFSM4I6NFFEQ .

[jrahmeh]

Fixed.