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westerndigitalcorporation / swerv_eh1_fpga

FPGA reference design for the the Swerv EH1 Core
Apache License 2.0
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getting error when Tcl script is executing in vivado 2018.2 #2

Closed mayank2016 closed 5 years ago

mayank2016 commented 5 years ago

Hello aprnath

I am trying to implement Swerv in Zedboard. On executing tcl script i am getting errors which is attached with this. tcl_console.txt

tcl console snippet: ERROR: [IP_Flow 19-3461] Value 'usb_uart' is out of the range for parameter 'UARTLITE BOARD INTERFACE(UARTLITE_BOARD_INTERFACE)' for BD Cell 'axi_uartlite_0' . Valid values are - Custom INFO: [IP_Flow 19-3438] Customization errors found on 'axi_uartlite_0'. Restoring to previous valid configuration. INFO: [Common 17-17] undo 'set_property' ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

while executing

"rdi::add_properties -dict {CONFIG.C_BAUDRATE 115200 CONFIG.C_S_AXI_ACLK_FREQ_HZ 40000000 CONFIG.C_S_AXI_ACLK_FREQ_HZ_d 40.0 CONFIG.UARTLITE_BOARD_INTE..." invoked from within "set_property -dict [ list CONFIG.C_BAUDRATE {115200} CONFIG.C_S_AXI_ACLK_FREQ_HZ {40000000} CONFIG.C_S_AXI_ACLK_FREQ_HZ_d {40.0} CONFIG.UARTLITE_B..." (procedure "cr_bd_axi_intc" line 94) invoked from within "cr_bd_axi_intc """ (file "/home/mayank/RISC5/swerv_eh1_fpga-master/hardware/project/script/nexys4ddr_refprj.tcl" line 745) update_compile_order -fileset sources_1

CONFIG.XBAR_DATA_WIDTH {64} \

] $axi_interconnect_0

Create instance: axi_uartlite_0, and set properties

set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]

set_property -dict [ list \

CONFIG.C_BAUDRATE {115200} \

CONFIG.C_S_AXI_ACLK_FREQ_HZ {40000000} \

CONFIG.C_S_AXI_ACLK_FREQ_HZ_d {40.0} \

CONFIG.UARTLITE_BOARD_INTERFACE {usb_uart} \

] $axi_uartlite_0

Create instance: blk_mem_gen_0, and set properties

set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]

set_property -dict [ list \

CONFIG.Enable_B {Use_ENB_Pin} \

CONFIG.Memory_Type {True_Dual_Port_RAM} \

CONFIG.Port_B_Clock {100} \

CONFIG.Port_B_Enable_Rate {100} \

CONFIG.Port_B_Write_Rate {50} \

CONFIG.Use_RSTB_Pin {true} \

] $blk_mem_gen_0

Create interface connections

connect_bd_intf_net -intf_net S00_AXI_0_1 [get_bd_intf_ports S00_AXI_0] [get_bd_intf_pins axi_interconnect_0/S00_AXI]

connect_bd_intf_net -intf_net S01_AXI_0_1 [get_bd_intf_ports S01_AXI_0] [get_bd_intf_pins axi_interconnect_0/S01_AXI]

connect_bd_intf_net -intf_net S02_AXI_0_1 [get_bd_intf_ports S02_AXI_0] [get_bd_intf_pins axi_interconnect_0/S02_AXI]

connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]

connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTB]

connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]

connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins axi_uartlite_0/S_AXI]

connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_ports UART_0] [get_bd_intf_pins axi_uartlite_0/UART]

Create port connections

connect_bd_net -net ACLK_0_1 [get_bd_ports ACLK_0] [get_bd_pins axi_interconnect_0/ACLK]

connect_bd_net -net ARESETN_0_1 [get_bd_ports ARESETN_0] [get_bd_pins axi_interconnect_0/ARESETN]

connect_bd_net -net S00_ACLK_0_1 [get_bd_ports S00_ACLK_0] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/S02_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk]

connect_bd_net -net S00_ARESETN_0_1 [get_bd_ports S00_ARESETN_0] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/S02_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn]

Create address segments

create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces S00_AXI_0] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0

create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces S01_AXI_0] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0

create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces S02_AXI_0] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0

create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces S00_AXI_0] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg

create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces S01_AXI_0] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg

create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces S02_AXI_0] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg

Restore current instance

current_bd_instance $oldCurInst

save_bd_design

close_bd_design $design_name

}

cr_bd_axi_intc ""

INFO: [BD_TCL-3] Currently there is no design in project, so creating one... Wrote : </home/mayank/nexys4ddr/nexys4ddr.srcs/sources_1/bd/axi_intc/axi_intc.bd> create_bd_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 6359.234 ; gain = 6.512 ; free physical = 5374 ; free virtual = 218683 INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog:
xilinx.com:ip:axi_bram_ctrl:4.0 xilinx.com:ip:axi_uartlite:2.0 xilinx.com:ip:blk_mem_gen:8.4 . INFO: [xilinx.com:ip:axi_bram_ctrl:4.0-2] axi_intc_axi_bram_ctrl_0_0: In IP Integrator, please note that memory depth value gets calculated based on the Data Width of the IP and Address range selected in the Address Editor.Incase a validation error occured on the range of this parameter, please check if the selected Data width and the Address Range are valid. For valid Data width and memory depth values, please refer to the AXI BRAM Controller Product Guide. INFO: [xilinx.com:ip:axi_bram_ctrl:4.0-1] axi_intc_axi_bram_ctrl_0_0: In IP Integrator, The Maximum address range supported is 2G. Selecting the address range more than 2G in the address editor may resets the value of Memory depth to default value (1024). please refer to the AXI BRAM Controller Product Guide. ERROR: [IP_Flow 19-3461] Value 'usb_uart' is out of the range for parameter 'UARTLITE BOARD INTERFACE(UARTLITE_BOARD_INTERFACE)' for BD Cell 'axi_uartlite_0' . Valid values are - Custom INFO: [IP_Flow 19-3438] Customization errors found on 'axi_uartlite_0'. Restoring to previous valid configuration. INFO: [Common 17-17] undo 'set_property' ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

while executing

"rdi::add_properties -dict {CONFIG.C_BAUDRATE 115200 CONFIG.C_S_AXI_ACLK_FREQ_HZ 40000000 CONFIG.C_S_AXI_ACLK_FREQ_HZ_d 40.0 CONFIG.UARTLITE_BOARD_INTE..." invoked from within "set_property -dict [ list CONFIG.C_BAUDRATE {115200} CONFIG.C_S_AXI_ACLK_FREQ_HZ {40000000} CONFIG.C_S_AXI_ACLK_FREQ_HZ_d {40.0} CONFIG.UARTLITE_B..." (procedure "cr_bd_axi_intc" line 94) invoked from within "cr_bd_axi_intc """ (file "/home/mayank/RISC5/swerv_eh1_fpga-master/hardware/project/script/nexys4ddr_refprj.tcl" line 745) update_compile_order -fileset sources_1

thanks & regards Mayank

arupde171 commented 5 years ago

Hi Mayank, Currently, the script only supports Nexys4 DDR board. You need to adapt the script for Zedboard.

Regards, Arup