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westerndigitalcorporation / swerv_eh1_fpga

FPGA reference design for the the Swerv EH1 Core
Apache License 2.0
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initializing issue while running the swerv core on zed board #8

Closed rajat-agnisys closed 4 years ago

rajat-agnisys commented 4 years ago

Hello,

I am just trying to run swerv design on xilinx zed board using vivado and instead of running it in the debug mode using jtag and uart, i want to interface this with zedboard io's. Could you help me in this as i am unable to write firmware sequences for the swerv core in fpga or how to initialize the memory with those hardcode sequence.

Thanks

arupde171 commented 4 years ago

Hi Rajat, You can check the firmware startup file to understand the firmware sequences after loading the program and reset the core.

Thanks, Arup