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wfjm / w11

PDP-11/70 CPU core and SoC
https://wfjm.github.io/home/w11/
GNU General Public License v3.0
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I have an ARTY S7 board, I'd like to try your w11 code. #38

Closed itoh5588 closed 1 year ago

itoh5588 commented 1 year ago

Hello , I'm an Japanese software engineer, I used to work for DEC Japan. I supported RSX-11M operation system and I did programming on it in Macro-11 and FORTRAN.

I'm VERY VERY interested in your w11 work. I hope your w11 code works on my ARTY S7.

I'm just an novice at FPGA, but I'm expert on UNIX/Linux. I published some books about PDP-11/UNIX/RSX-11 on Rapsberry Pi using SIMH in Amazon Kindle book store.

Your project have a lot of information and I'm lost, so would you help me?

wfjm commented 1 year ago

related to #17

wfjm commented 1 year ago

Hi @itoh5588,
nice to hear about your interest in the w11 project !

The project has a design for the Arty S7 board under rtl/sys_gen/w11a/artys7.
This design was only simulation tested (see #17), but given that this board is very similar to the Arty A7 chances are very high that it works also on the FPGA. The design is for the 50 die size. Do you have that board version ?

Did you have a look at the quickstart guide ? That explains the requirements for the Arty A7 case and should, apart from some path names, in principle be valid for the Arty S7 case. In case of problems with the DDR memory, there is also a BRAM-only design, but that offers only 256kB system memory, enough for plain RSX-11M, but insufficient for 211BSD and RSX-11M+.

I strongly suggest verifying the port to FPGA pin mapping. I haven't checked against the latest board revision, and for obvious reasons, I never did a smoke check myself.

Last but not least you'll find a general description of the currently implemented functionality under https://wfjm.github.io/home/w11/.

itoh5588 commented 1 year ago

Hello , Mr. Mueller. Thanks for such a quick reply !

I'll follow your instructions and if I have some questions , would you help me ?.

I appreciate your help very much.

Akio Itoh

2023年1月23日(月) 3:46 Walter F.J. Mueller @.***>:

Hi @itoh5588 https://github.com/itoh5588, nice to hear about your interest in the w11 project !

The project has a design for the Arty S7 board under rtl/sys_gen/w11a/artys7 https://github.com/wfjm/w11/tree/master/rtl/sys_gen/w11a/artys7. This design was only simulation tested (see #17 https://github.com/wfjm/w11/issues/17), but given that this board is very similar to the Arty A7 chances are very high that it works also on the FPGA. The design is for the 50 die size. Do you have that board version ?

Did you have a look at the quickstart guide https://github.com/wfjm/w11/blob/master/doc/INSTALL_quickstart.md ? That explains the requirements for the Arty A7 case and should, apart from some path names, in principle be valid for the Arty S7 case. In case of problems with the DDR memory, there is also a BRAM-only design, but that offers only 256kB system memory, enough for plain RSX-11M, but insufficient for 211BSD and RSX-11M+.

I strongly suggest verifying the port to FPGA pin mapping. I haven't checked against the latest board revision, and for obvious reasons, I never did a smoke check myself.

Last but not least you'll find a general description of the currently implemented functionality under https://wfjm.github.io/home/w11/.

— Reply to this email directly, view it on GitHub https://github.com/wfjm/w11/issues/38#issuecomment-1399572023, or unsubscribe https://github.com/notifications/unsubscribe-auth/AANUC4BCKK2I37CXB7OLJS3WTV6A5ANCNFSM6AAAAAAUCEGDLY . You are receiving this because you were mentioned.Message ID: @.***>

wfjm commented 1 year ago

Hello Akio,

sure ! w11 is a non-trivial Vivado build, and operating the design requires quite some infrastructure.
That's certainly not a good starter project for a newly purchased board.
So I assume that you did some some 'blinking LED' type designs first to verify the basics.

itoh5588 commented 1 year ago

Hi, Thank you . Yes I need some very basic practices on ARTY S7 and I'll go forward step by step. Akio.

2023年1月23日(月) 17:15 Walter F.J. Mueller @.***>:

Hello Akio,

sure ! w11 is a non-trivial Vivado build, and operating the design requires quite some infrastructure. That's certainly not a good starter project for a newly purchased board. So I assume that you did some some 'blinking LED' type designs first to verify the basics.

— Reply to this email directly, view it on GitHub https://github.com/wfjm/w11/issues/38#issuecomment-1399952404, or unsubscribe https://github.com/notifications/unsubscribe-auth/AANUC4BKKBO2L3T4AE2Q6ATWTY43JANCNFSM6AAAAAAUCEGDLY . You are receiving this because you were mentioned.Message ID: @.***>

wfjm commented 1 year ago

I'll close this issue for the time being.
You are very welcome to re-open it in case new questions come up from your side.

itoh5588 commented 1 year ago

Hello, thanks for your support. I'm learning Vivado 2022. If I need your support , I re-open it.

2023年1月30日(月) 2:55 Walter F.J. Mueller @.***>:

I'll close this issue for the time being. You are very welcome to re-open it in case new questions come up from your side.

— Reply to this email directly, view it on GitHub https://github.com/wfjm/w11/issues/38#issuecomment-1407728711, or unsubscribe https://github.com/notifications/unsubscribe-auth/AANUC4EFFQC5IW75FJ4MMVLWU2VKNANCNFSM6AAAAAAUCEGDLY . You are receiving this because you were mentioned.Message ID: @.***>

wfjm commented 1 year ago

Also keep in mind, that the w11 are not (yet) standalone systems.
For the overall concept see

and especially how the IO system is implemented

As said before, w11 designs are not stand-alone systems, they rely on a backend server and a high-speed, low latency connection.

itoh5588 commented 1 year ago

Oh! I didn't notice that, it's a very good idea. The CPU is on FPGA and all peripherals are on a server. All CPU textbooks in VHDL are only CPU implementations.

I understand your design.

Thanks very much!

Akio Itoh.

2023年2月2日(木) 16:46 Walter F.J. Mueller @.***>:

Also keep in mind, that the w11 are not (yet) standalone systems. For the overall concept see

and especially how the IO system is implemented

As said before, w11 designs are not stand-alone systems, they rely on a backend server and a high-speed, low latency connection.

— Reply to this email directly, view it on GitHub https://github.com/wfjm/w11/issues/38#issuecomment-1413284850, or unsubscribe https://github.com/notifications/unsubscribe-auth/AANUC4FNDPGWSFJEFBMWP43WVNQ6ZANCNFSM6AAAAAAUCEGDLY . You are receiving this because you were mentioned.Message ID: @.***>

wfjm commented 1 year ago

Well, on the long run I'd like to have a w11 that operates either stand-alone or at least without a permanent USB connection. I want to keep the HDL of the devices simple, as it is now. So one needs a processor that handles the mapping of all the legacy devices to modern real ones. And I want to stay 'retro' on the FPGA side. The obvious solution is to instantiate a second w11 core as CIOP (console and IO processor). That's quite straight-forward to implement with the available components and a modest amount of new ones. The CIOP will run 'bare metal' code, no underlying OS. Could be build like a 2.11BSD system image and leverage this infrastructure. No essential show stoppers, all well doable, and stays nicely in the retro corner. The direction is clear, but it'll take some time to implement both VHDL and the CIOP code (now in C for the 2.11BSD C compiler).