Redsea should recover the clock signal and integrate over the DPSK bit-time to ensure best SNR. Currently there is no locking whatsoever and the signal will fade in and out at the difference frequency between TX and RX clocks.
Suggested fix: PLL
This locking could be implemented as a PLL. There is a PLL readily available in liquid-dsp.
Caveat
How to present an estimate of the phase error to the PLL in the presence of gradual 180-degree phase shifts?
Suggested fix: symsync
There's also a symbol synchronizer in liquid that probably does everything needed for carrier & clock recovery
Caveat
How to use it in binary DPSK? The example for QPSK does not work for RDS.
Redsea should recover the clock signal and integrate over the DPSK bit-time to ensure best SNR. Currently there is no locking whatsoever and the signal will fade in and out at the difference frequency between TX and RX clocks.
Suggested fix: PLL
This locking could be implemented as a PLL. There is a PLL readily available in liquid-dsp.
Caveat
How to present an estimate of the phase error to the PLL in the presence of gradual 180-degree phase shifts?
Suggested fix: symsync
There's also a symbol synchronizer in liquid that probably does everything needed for carrier & clock recovery
Caveat
How to use it in binary DPSK? The example for QPSK does not work for RDS.