FPGAs limit performance based on average server time (rolling average). This works fine for the most of the time, but servers can spike for some time, crashing FPGAs because they suddenly use up 3 to 5 times more server time per second.
I believe this is the reason E2 limits based on OPS, maybe something similar could be done here? Limit based on 'gate calculations' (each node being processed would be one calculation, even if the input hasn't arrived yet)
FPGAs limit performance based on average server time (rolling average). This works fine for the most of the time, but servers can spike for some time, crashing FPGAs because they suddenly use up 3 to 5 times more server time per second.
I believe this is the reason E2 limits based on OPS, maybe something similar could be done here? Limit based on 'gate calculations' (each node being processed would be one calculation, even if the input hasn't arrived yet)