[feature] Netlist input/output

[aakatz3]

It would be nice to have an output and/or input for some form of EDA type netlist, whether in SPICE type format, Protel/Altium format, Kicad format, eagle format, etc.

If people want this feature, I can investigate to see which format is the best.

[formatc1702]

I hadn't thought of any EDA tool integration (could you describe a specific usecase for this?) but a sort of netlist output has been on my mind.

Simply a table of signals within the harness, and a listing of which wires and connector pins are carrying this signal, would be quite useful when the wiring diagram gets a bit more complex and individual wires harder to follow.

Example output shown as YAML for readability>

netlist:
  GND:
    - X1: [1, 3]
    - W1: [1, s]
    - X2: [1]
  VCC:
    - X1: [2]
    - W1: [2]
    - X2: [2]

This would obviously be separate from any pin labels (classic example: RX/TX crossover would cause issues), so signal names would have to be defined elsewhere. I guess we'd need an expert on graph theory to follow a signal thats labeled once (e.g. on any random connector's pin) along all wires, loops, etc. and make sure there are no "shorts" between differently labeled nets/signals.

I'm not sure how a netlist input would work?

[aakatz3]

If you draw schematics for connectors in something like altium or kicad, and wish to migrate or better visualize them in wireviz, you may export a netlist:

• Kicad Netlist

• Protel Netlist

• SPICE Netlist

• Orcad Netlist

There are an absolute buttload of formats, but essentially, netlist import would allow wireviz to be able to import and export from schematics from eda tools, or at least spice or tinycad schematics.

Ideally, Wireviz would be able to generate its own format of YML file from the netlist to allow for all of the options it supports to be used.

On another note: while I love your YAML styled netlist, sadly no existing tool can take that as either an input or generate it as an output, though it is somewhat close to existing ones!

[stevegt]

The PySpice netlist parser might be worth experimenting with: https://github.com/FabriceSalvaire/PySpice/blob/319d300fb5f18fc4800d4282c39b2e348d167695/PySpice/Spice/Parser.py#L772

[martinrieder]

Some more possibilities here:

• tscircuit/kicad-mod-converter This module converts kicad files into a tscircuit soup json, an easy-to-use JSON format for electronics.
• jdthorpe/kicad-module-parser Convert your Kicad board and module files to JSON or YAML and use your favorite tools to work with your Kicad board and module file data!
• CatoLynx/kicad-mod2openpnp Python tool to convert KiCad (.kicad_mod) footprint pad definitions to OpenPnP package XML
• benwaeseperlman/KiCad-Converters Converters from the LTspice .asy symbol file format to KiCad Libraries and from the FreePCB .fpl footprint file format to KiCad .pretty folders and .KiCad_mod files

Intro on the KiCAD S-Expression Format

PS: Using this method would also allow defining some pinout diagrams as requested in #27.