Open ask6483 opened 1 year ago
Thank you for reporting your use case. This must be a simple bug, was my first impression, and I quickly located two code locations where I added one extra indentation level to make them part of the if not ignore_in_bom:
block just above.
https://github.com/wireviz/WireViz/blob/v0.3.2/src/wireviz/wv_bom.py#L83-L84 https://github.com/wireviz/WireViz/blob/v0.3.2/src/wireviz/wv_bom.py#L114-L115
That simple fix described above does indeed what you ask for, but only if options.mini_bom_mode
is False, and the default value is True. When options.mini_bom_mode
is True, then any list of additional components in the diagram nodes are supposed to contain the BOM entry IDs as a reference for more information details. That code fails with an exception when there is no matching entry in the BOM. We need to decide how to handle such a conflict.
options.mini_bom_mode
is True.options.mini_bom_mode
for additional components that are hidden from the BOM.@ask6483, do you also request controlling ignore_in_bom
for each additional component? That would enable ignoring any combination of connector/cable entry and additional component entries in the BOM. However, the same conflicts as described above, still exist, and must be handled.
Is it possible to also ignore additional components in bom generation? For example ignore_in_bom will hide connector housing but not crimp terminals:
I want to create cable diagram but the part is available as pre-crimped wire so there is only one item in bom.