Core1 support

[mingpepe]

Is any plan to do this?

[urish]

Seems like Core1 is not widely used - other than you, I think only one person asked about it to date.

Do you have any concrete use case for simulating Core1?

[mingpepe]

I want to emulate my code and core1 is part of it.

Indeed not many projects use core1 or just use it to do trivial task, but I think core1 is important if you care about performance.

It's ok not having a schedule for this because I am working in progress but it's not a trivial task and some details I do not understand. I will post what I have done and problems later, some suggestions may be helpful.

[urish]

Got it.

We did some preparation at 29746d1e02ff04680809dde23981a351bdd7826c. I think the next step would be:

1. Change core into an array of two cores. Then in step(), call executeInstruction on each of the cores. Also in reset(), reset both cores.
2. Implement SIO FIFOs (so the two cores can talk), and make sure each core gets its own cpuid, interpolator and integer divider units:
3. Making sure that interrupts are routed to the right core. In particular, GPIO has core-specific interrupts (and there's also SIO_IRQ_PROC0/SIO_IRQ_PROC1 which I'm not sure about)

That's from the top of my head.

[urish]

Regarding the popularity of this feature: I've opened it for voting back in August. I just checked the votes status, seems like nobody voted for it so far.

[mingpepe]

:smiling_face_with_tear:

[mingpepe]

Currently works fine for basic samples hello_multicore multicore_runner multicore_runner_queue

But still not working for interrupt handling multicore_fifo_irqs