Closed dgarske closed 3 years ago
@dgarske I am ready to merge this, I just want to confirm there is nothing more to be added in this PR?
I am asking because I saw "SPI check wait state logic" mentioned in the description and could not see a change about the wait logic.
@dgarske I am ready to merge this, I just want to confirm there is nothing more to be added in this PR?
I am asking because I saw "SPI check wait state logic" mentioned in the description and could not see a change about the wait logic.
Yes ready to go. The addition of the SPI wait state eliminated the old logic and made txBuf[4] = 0x00;
dead code that I removed.
txBuf[4] = 0x00;
replaced with SPI check wait state logic. TheTPM_TIS_HEADER_SZ
is always 4.