for loop expansion

[xuliangfei3]

It seems not support the for loop expansion. Is my usage incorrect, or is it really not supported?

like this: <% for( $i = 0; $i < 4; $i += 1) { %>

May I ask for your help？thks~~~

[udif]

Judging from what I see if the source code, this is a pure Verilog preprocessor. It only processes the C-like backtick macro commands ( `define, `ifdef, etc.) and the so-called industry "standard" translate on/off comments (should have been abandoned many years ago).

What you are looking for is Apache::ASP style preprocessing, as typically used by SystemRDL.

Try looking here: https://github.com/gxwcxl2010/System-RDL-preprocess

[xuliangfei3]

Judging from what I see if the source code, this is a pure Verilog preprocessor. It only processes the C-like backtick macro commands (define,ifdef, etc.) and the so-called industry "standard" translate on/off comments (should have been abandoned many years ago).

What you are looking for is Apache::ASP style preprocessing, as typically used by SystemRDL.

Try looking here: https://github.com/gxwcxl2010/System-RDL-preprocess

OK, thank you for your guidance

[wsong83]

I think @udif is right. Only macros of the standard Verilog HDL are supported. If any new features need to be added, the first thing to check is to see whether it is already supported by the original Verilog-Perl package (https://metacpan.org/pod/vppreproc) because this project is just a C++ wrapper of the perl package with some tweaks.

Anyway, thanks for your interst in this rather old project.

[xuliangfei3]

Thank you for your patient guidance! I refer to the Perl script you sent me last time（ https://github.com/gxwcxl2010/System-RDL-preprocess ) The for loop is expanded by generating an intermediate *. PL script and printing circularly in the script.