wuxx / icesugar-nano

iCESugar-nano FPGA board (base on iCE40LP1K)
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uart echo example not working? #11

Closed haaslukas closed 9 months ago

haaslukas commented 9 months ago

I'd like to add a uart feature to my project and first wanted to test the uart echo code from the demo repo here I flashed the .bin file to the icesugar-nano and connected via the CoolTerm terminal application (baudrate 115200, 8 data bits, no parity, 1 stop bit). when sending data I see the led flickering on the icesugar-nano. so something seems to arrive. but I'm not getting any readable symbols back despite seeing some Rx coming in on the CoolTerm. I also build the project myself with apio and doing the direct loopback assign TX = RX;, but even then I don't see any "useful" data coming back. I also tried different terminal applications like putty or a screen command on linux. the same problem everywhere. any idea how to continue or fix the code? did anyone got the uart echo example to work?

haaslukas commented 9 months ago

ok, never mind. just found the bug. need to activate line mode in the terminal in order to see the data coming back on the RX line. and I'm also able to build with apio, but needed to change the code slightly:

`include "uart_rx.v"
`include "uart_tx.v"

module top (
    input CLK,
    input RX,
  output TX,
    output reg LED
);

wire clk_42mhz;

/* local parameters */
localparam clk_freq = 12_000_000; // 12MHz
//localparam clk_freq = 42_000_000; // 42MHz
//localparam baud = 57600;
localparam baud = 115200;

/* instantiate the rx1 module */
wire rx1_ready;
wire [7:0] rx1_data;
uart_rx #(clk_freq, baud) urx1 (
    .clk(CLK),
    .rx(RX),
    .rx_ready(rx1_ready),
    .rx_data(rx1_data)
);

/* instantiate the tx1 module */
reg tx1_start;
reg [7:0] tx1_data;
wire tx1_busy;
uart_tx #(clk_freq, baud) utx1 (
    .clk(CLK),
    .tx_start(tx1_start),
    .tx_data(tx1_data),
    .tx(TX),
    .tx_busy(tx1_busy)
);

// Send the received data immediately back

reg [7:0] data_buf;
reg data_flag = 0;
reg data_check_busy = 0;
always @(posedge CLK) begin

  // we got a new data strobe
  // let's save it and set a flag
    if(rx1_ready && ~data_flag) begin
    data_buf <= rx1_data;
    data_flag <= 1;
    data_check_busy <= 1;
  end

  // new data flag is set let's try to send it
  if(data_flag) begin

    // First check if the previous transmission is over
    if(data_check_busy) begin
      if(~tx1_busy) begin
        data_check_busy <= 0;
      end // if(~tx1_busy)

    end else begin // try to send waiting for busy to go high to make sure
      if(~tx1_busy) begin
        tx1_data <= data_buf;
        tx1_start <= 1'b1;
        //LED_R <= ~data_buf[0];
        //LED_G <= ~data_buf[1];
        LED <= ~data_buf[1];
      end else begin // Yey we did it!
        tx1_start <= 1'b0;
        data_flag <= 0;
      end
    end
  end
end

// Loopback the TX and RX lines with no processing
// Useful as a sanity check ;-)
//assign TX = RX;

endmodule