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wwylele / teakra

DSi/3DS DSP emulator, disassembler, assembler, and tester
MIT License
76 stars 19 forks source link

The timer frequency is incorrect #47

Open wwylele opened 4 years ago

wwylele commented 4 years ago

After looking at the timer stuff in perxteak.per, I figured that they are both having different internal clocks. I had only tested timer 1 yet, but when testing both timers... Timer 0 is 134MHz (called "internal clock with no wait-states") Timer 1 is 107MHz (called "internal clock with wait-states") No idea where those wait-states come from, and if they are constant. It might be something else than the Z0/Z1/Z2/Z3 area wait-states. Another difference (not mentioned in the .per file) is that Timer 1 seems to have the MU bit always set (the bit is readonly).