Currently auto generated VHDL functions converting to std_logic_vector type have following format {type_name}2stlv.
This is superfluous clutter. VHDL allows ad hoc polymorphism via function overloading.
[x] Functions converting to std_logic_vector should be named to_slv. The same way it is done in the standard libraries.
[x] The same applies to the functions converting to the custom types. Instead of stlv2{type_name} it should be to_{type_name}.
Currently auto generated VHDL functions converting to
std_logic_vectortype have following format{type_name}2stlv. This is superfluous clutter. VHDL allows ad hoc polymorphism via function overloading.[x] Functions converting to
std_logic_vectorshould be namedto_slv. The same way it is done in the standard libraries.[x] The same applies to the functions converting to the custom types. Instead of
stlv2{type_name}it should beto_{type_name}.