where to find the weights and bias files?

[218w1d7706]

@xbdxwyh hello, help me to get the files of weights and bias. thank you.

[xbdxwyh]

Hi, I'm not sure which weights and bias you need. If you need YOLOV3 original weights and bias, you can find them on the official website. If you need the processed weights and bias, then I'm sorry, I don't have this file saved. But this repository is for converting the raw YOLOV3 weights and bias to run on FPGAs. If you are still new to this process, refer to the YOLOV2 repository below. My repository is based on the changes implemented in this YOLOV2 repository.

[218w1d7706]

@xbdxwyh thank you for the response, actually we can download weights from official site(yolo). can i use those weights directly ? and i'm unable to find bias file.

[xbdxwyh]

Our repository is used to convert the raw official yolo weights to weights that are runnable on FPGAs. The official weights are decomposed into two files, weights and bias, by stepwise disassembly and quantization of the code in this repository. The order of weights separation and quantization is in the softversion folder with the code. For this process, you can refer to this repository. I did not modify the separation code but used the code in yolov2_xilinx_fpga/software_version/01_ExtractWeightAndBiasFromDarknet directly.

After the weight decomposition and quantization are done, the core code is compiled in the yolov3_hls folder, and the final runnable on-chip program is in the yolov3_elf folder.

[218w1d7706]

@218w1d7706 thank you so much for the response, I'll follow the links you referred. thank you.

[218w1d7706]

@xbdxwyh hello, my resources utilization are exceeding than the available resources. any suggestions to reduce the resource utilization. btw i'm using zedboard. thank you

[xbdxwyh]

Hi, I don't know how to reduce resources under zedboard either since I'm using Zynq. Still, you could consider further reducing the number of bits for weight quantization, for example, INT4 or INT8, but I haven't implemented those.

[218w1d7706]

@xbdxwyh thank you for suggestion. i did overcome the resource problem and completed the work upto bitstream generation, how do i proceed further?please suggest a flow to how i proceed further? do i have to use sdk or petalinux or both for fpga deployment. thank you. if you dont mind can you share your socials to connect with you easily. thank you

[xbdxwyh]

If by bitstream you mean the bitstream of the HLS core, then after generating the bitstream, you need to introduce this HLS core in the vivado project https://github.com/dhm2013724/yolov2_xilinx_fpga/tree/flex/vivado and follow this process to generate the constraints The next step is to generate the SDK.

The next step is to generate a runnable SDK program and use pentalinux to generate the overall system for on-chip burn-in. After the burn is complete, upload your processed Weights and bin files, and once these are complete, you are ready to run.

If by bitstream you mean the bitstream generated by pentalinux and there are no problems, then after burning, you only need to generate the runnable SDK program, see https://github.com/dhm2013724/yolov2_xilinx_fpga/tree/flex/SDK and upload the weights and bias files to run it.

Regarding social accounts, you can refer to the following question https://github.com/dhm2013724/yolov2_xilinx_fpga/issues/73

Here is a wechat group for communication and discussion

[218w1d7706]

@xbdxwyh i'm getting error at build phase of petalinux. internet is stable but dont no when the errors are occuring. can we use only SDK to lauch the hardware into fpga. if yes, please link me to that tutorial. i'm from india so unable to connect in wechat any other socials like linkedin,fb, any other platforms..