xbdxwyh / yolov3_fpga_project

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what is the process after generating bitstream? #24

Open 218w1d7706 opened 1 year ago

218w1d7706 commented 1 year ago

@xbdxwyh i have done the flow upto bitstream generation. after that how i can implement the exported hardware to fpga? i did verified mr chen chen's repo but i cant understand the sdk and petalinux directories. can you help me with this issue? thankyou.

xbdxwyh commented 1 year ago

The core of HLS, you can understand it as a program to manipulate the FPGA gates, after this step you just get the corresponding part of the design, it doesn't mean it's a complete runnable program, because you still need to handle the inputs and outputs.

After completing the HLS, you need to refer to the vivado project to connect this core with the complete input and output system. https://github.com/dhm2013724/yolov2_xilinx_fpga/tree/flex/vivado

And these steps are only at the hardware level, you still need an operating system to support your software part, the so called petalinux part is to implement such a system, an operating system that matches the core you have designed.

The SDK part, on the other hand, is to generate a program that actually utilizes the HLS core and can be understood by the OS. You can think of HLS as the hardware side, and the SDK as the software side.