xbdxwyh
commented
1 month ago Hi, this job was a long time ago so I can only provide some general information.
There are basically two key steps in the mapping process, mainly in the computational units of the IP cores (e.g. convolution, addition, etc.), and if a higher version has additional computational units, you will need to add the corresponding computations here. The second is the memory management on-chip, different versions use different layers of the pyramid, so you need to design separate memory management to make them work correctly. I.e. each layer calls the correct computing core. As for the rest of the details, you can learn them in the xilinx related material. I've uploaded some Chinese documentation for these details, including my reproduction of the v2 version and some of the design of my version (in pdf format).
For similar work, xilinx has some basic tutorials. There is also some official documentation for learning, though I can't remember the exact numbered code. Also, I think you can find similar tutorials on some video sites.
As for the code, my work is based on the v2 version by Chen et al, although chen has updated it several times in the following. https://github.com/dhm2013724/yolov2_xilinx_fpga
As for the rest of the details, I'm no longer working in that direction and I'm sorry I can't help you more.
hey @xbdxwyh, can you please provide the resources for how we can map yolo to hls. any references, sources or what's the direction of work. thank you.