Stumbled upon this when I was playing with setting PHY mode to fixed 100M baseT on the mode pins, and was unable to set to autoneg in software.
As with so many things in life, found that PHY just wasn't ready to listen. A quick check on AVB-LC board shows about a millisecond of polling before power down bit is cleared and PHY is configured, so not a major delay.
Stumbled upon this when I was playing with setting PHY mode to fixed 100M baseT on the mode pins, and was unable to set to autoneg in software.
As with so many things in life, found that PHY just wasn't ready to listen. A quick check on AVB-LC board shows about a millisecond of polling before power down bit is cleared and PHY is configured, so not a major delay.