Segmentation fault on a channel event

jameshanlon commented 13 years ago

When a channel event is raised in the simulation of a G4 device (XC-1) it seg-faults:

$ sire test/features/on_basic.sire -n 4 $ axe a.xe Segmentation fault $ xsim a.xe DEADBEEF

This doesn't seem to happen with an XMP-64 (or other systems I'm testing):

$ sire test/features/on_basic.sire -n 64 $ axe a.xe DEADBEEF $ xsim a.xe DEADBEEF

Here's the full trace:

$ axe a.xe -t [c0t0] _start(0x10aea): [c1t0] _start(0x10ac4): [c2t0] _start(0x10ac4): [c3t0] _start(0x10ac4): [c3t0] touchRegs(0x1007a): [c3t0] touchRegs+2(0x1007c): [c3t0] touchRegs+4(0x1007e): [c3t0] touchRegs+6(0x10080): [c3t0] touchRegs+8(0x10082): [c3t0] touchRegs+10(0x10084): [c3t0] touchRegs+12(0x10086): [c3t0] touchRegs+14(0x10088): [c3t0] touchRegs+16(0x1008a): [c3t0] touchRegs+18(0x1008c): [c3t0] touchRegs+20(0x1008e): [c3t0] touchRegs+22(0x10090): [c0t0] touchRegs(0x1007a): [c0t0] touchRegs+2(0x1007c): [c0t0] touchRegs+4(0x1007e): [c0t0] touchRegs+6(0x10080): [c0t0] touchRegs+8(0x10082): [c0t0] touchRegs+10(0x10084): [c0t0] touchRegs+12(0x10086): [c0t0] touchRegs+14(0x10088): [c0t0] touchRegs+16(0x1008a): [c0t0] touchRegs+18(0x1008c): [c0t0] touchRegs+20(0x1008e): [c0t0] touchRegs+22(0x10090): [c1t0] touchRegs(0x1007a): [c1t0] touchRegs+2(0x1007c): [c1t0] touchRegs+4(0x1007e): [c1t0] touchRegs+6(0x10080): [c1t0] touchRegs+8(0x10082): [c1t0] touchRegs+10(0x10084): [c1t0] touchRegs+12(0x10086): [c1t0] touchRegs+14(0x10088): [c1t0] touchRegs+16(0x1008a): [c1t0] touchRegs+18(0x1008c): [c1t0] touchRegs+20(0x1008e): [c1t0] touchRegs+22(0x10090): [c2t0] touchRegs(0x1007a): [c2t0] touchRegs+2(0x1007c): [c2t0] touchRegs+4(0x1007e): [c2t0] touchRegs+6(0x10080): [c2t0] touchRegs+8(0x10082): [c2t0] touchRegs+10(0x10084): [c2t0] touchRegs+12(0x10086): [c2t0] touchRegs+14(0x10088): [c2t0] touchRegs+16(0x1008a): [c2t0] touchRegs+18(0x1008c): [c2t0] touchRegs+20(0x1008e): [c2t0] touchRegs+22(0x10090): [c2t0] _start+4(0x10ac8): [c3t0] _start+4(0x10ac8): [c0t0] _start+4(0x10aee): [c1t0] _start+4(0x10ac8): [c1t0] initMemory(0x1013c): [c1t0] initMemory+4(0x10140): [c1t0] initMemory+6(0x10142): [c1t0] initMemory+10(0x10146): [c1t0] initMemory+12(0x10148): [c1t0] initMemory+14(0x1014a): [c1t0] initMemory+16(0x1014c): [c1t0] initMemory+18(0x1014e): [c1t0] initMemory+20(0x10150): [c1t0] initMemory+22(0x10152): [c1t0] initMemory+26(0x10156): [c1t0] initMemory+30(0x1015a): [c1t0] initMemory+32(0x1015c): [c1t0] initMemory+34(0x1015e): [c2t0] initMemory(0x10140): [c2t0] initMemory+4(0x10144): [c2t0] initMemory+6(0x10146): [c2t0] initMemory+10(0x1014a): [c2t0] initMemory+12(0x1014c): [c2t0] initMemory+14(0x1014e): [c2t0] initMemory+16(0x10150): [c2t0] initMemory+18(0x10152): [c2t0] initMemory+20(0x10154): [c2t0] initMemory+22(0x10156): [c2t0] initMemory+26(0x1015a): [c2t0] initMemory+30(0x1015e): [c2t0] initMemory+32(0x10160): [c2t0] initMemory+34(0x10162): [c3t0] initMemory(0x10140): [c3t0] initMemory+4(0x10144): [c3t0] initMemory+6(0x10146): [c3t0] initMemory+10(0x1014a): [c3t0] initMemory+12(0x1014c): [c3t0] initMemory+14(0x1014e): [c3t0] initMemory+16(0x10150): [c3t0] initMemory+18(0x10152): [c3t0] initMemory+20(0x10154): [c3t0] initMemory+22(0x10156): [c3t0] initMemory+26(0x1015a): [c3t0] initMemory+30(0x1015e): [c3t0] initMemory+32(0x10160): [c3t0] initMemory+34(0x10162): [c0t0] initMemory(0x1013c): [c0t0] initMemory+4(0x10140): [c0t0] initMemory+6(0x10142): [c0t0] initMemory+10(0x10146): [c0t0] initMemory+12(0x10148): [c0t0] initMemory+14(0x1014a): [c0t0] initMemory+16(0x1014c): [c0t0] initMemory+18(0x1014e): [c0t0] initMemory+20(0x10150): [c0t0] initMemory+22(0x10152): [c0t0] initMemory+26(0x10156): [c0t0] initMemory+30(0x1015a): [c0t0] initMemory+32(0x1015c): [c0t0] initMemory+34(0x1015e): [c0t0] initMemory+26(0x10156): [c0t0] initMemory+30(0x1015a): [c0t0] initMemory+32(0x1015c): [c0t0] initMemory+34(0x1015e): [c1t0] initMemory+26(0x10156): [c1t0] initMemory+30(0x1015a): [c1t0] initMemory+32(0x1015c): [c1t0] initMemory+34(0x1015e): [c2t0] initMemory+26(0x1015a): [c2t0] initMemory+30(0x1015e): [c2t0] initMemory+32(0x10160): [c2t0] initMemory+34(0x10162): [c3t0] initMemory+26(0x1015a): [c3t0] initMemory+30(0x1015e): [c3t0] initMemory+32(0x10160): [c3t0] initMemory+34(0x10162): [c3t0] initMemory+26(0x1015a): [c3t0] initMemory+30(0x1015e): [c3t0] initMemory+32(0x10160): [c3t0] initMemory+34(0x10162): [c3t0] initMemory+36(0x10164): [c0t0] initMemory+26(0x10156): [c0t0] initMemory+30(0x1015a): [c0t0] initMemory+32(0x1015c): [c0t0] initMemory+34(0x1015e): [c1t0] initMemory+26(0x10156): [c1t0] initMemory+30(0x1015a): [c1t0] initMemory+32(0x1015c): [c1t0] initMemory+34(0x1015e): [c1t0] initMemory+36(0x10160): [c2t0] initMemory+26(0x1015a): [c2t0] initMemory+30(0x1015e): [c2t0] initMemory+32(0x10160): [c2t0] initMemory+34(0x10162): [c2t0] initMemory+36(0x10164): [c0t0] initMemory+26(0x10156): [c0t0] initMemory+30(0x1015a): [c0t0] initMemory+32(0x1015c): [c0t0] initMemory+34(0x1015e): [c3t0] initMemory+24(0x10158): [c1t0] initMemory+24(0x10154): [c2t0] initMemory+24(0x10158): [c2t0] _start+8(0x10acc): [c3t0] _start+8(0x10acc): [c1t0] _start+8(0x10acc): [c1t0] initPointers(0x10048): [c1t0] initPointers+4(0x1004c): [c1t0] initPointers+6(0x1004e): [c1t0] initPointers+10(0x10052): [c1t0] initPointers+12(0x10054): [c1t0] initPointers+14(0x10056): [c1t0] initPointers+18(0x1005a): [c1t0] initPointers+22(0x1005e): [c1t0] initPointers+26(0x10062): [c1t0] initPointers+28(0x10064): [c1t0] initPointers+30(0x10066): [c1t0] initPointers+32(0x10068): [c1t0] initPointers+34(0x1006a): [c1t0] initPointers+36(0x1006c): [c1t0] initPointers+40(0x10070): [c1t0] initPointers+42(0x10072): [c1t0] initPointers+44(0x10074): [c1t0] initPointers+48(0x10078): [c0t0] initMemory+26(0x10156): [c0t0] initMemory+30(0x1015a): [c0t0] initMemory+32(0x1015c): [c0t0] initMemory+34(0x1015e): [c2t0] initPointers(0x10048): [c2t0] initPointers+4(0x1004c): [c2t0] initPointers+6(0x1004e): [c2t0] initPointers+10(0x10052): [c2t0] initPointers+12(0x10054): [c2t0] initPointers+14(0x10056): [c2t0] initPointers+18(0x1005a): [c2t0] initPointers+22(0x1005e): [c2t0] initPointers+26(0x10062): [c2t0] initPointers+28(0x10064): [c2t0] initPointers+30(0x10066): [c2t0] initPointers+32(0x10068): [c2t0] initPointers+34(0x1006a): [c2t0] initPointers+36(0x1006c): [c2t0] initPointers+40(0x10070): [c2t0] initPointers+42(0x10072): [c2t0] initPointers+44(0x10074): [c2t0] initPointers+48(0x10078): [c3t0] initPointers(0x10048): [c3t0] initPointers+4(0x1004c): [c3t0] initPointers+6(0x1004e): [c3t0] initPointers+10(0x10052): [c3t0] initPointers+12(0x10054): [c3t0] initPointers+14(0x10056): [c3t0] initPointers+18(0x1005a): [c3t0] initPointers+22(0x1005e): [c3t0] initPointers+26(0x10062): [c3t0] initPointers+28(0x10064): [c3t0] initPointers+30(0x10066): [c3t0] initPointers+32(0x10068): [c3t0] initPointers+34(0x1006a): [c3t0] initPointers+36(0x1006c): [c3t0] initPointers+40(0x10070): [c3t0] initPointers+42(0x10072): [c3t0] initPointers+44(0x10074): [c3t0] initPointers+48(0x10078): [c0t0] initMemory+26(0x10156): [c0t0] initMemory+30(0x1015a): [c0t0] initMemory+32(0x1015c): [c0t0] initMemory+34(0x1015e): [c0t0] initMemory+26(0x10156): [c0t0] initMemory+30(0x1015a): [c0t0] initMemory+32(0x1015c): [c0t0] initMemory+34(0x1015e): [c0t0] initMemory+26(0x10156): [c0t0] initMemory+30(0x1015a): [c0t0] initMemory+32(0x1015c): [c0t0] initMemory+34(0x1015e): [c0t0] initMemory+26(0x10156): [c0t0] initMemory+30(0x1015a): [c0t0] initMemory+32(0x1015c): [c0t0] initMemory+34(0x1015e): [c1t0] _start+12(0x10ad0): [c2t0] _start+12(0x10ad0): [c3t0] _start+12(0x10ad0): [c3t0] setupTraps(0x10092): [c3t0] setupTraps+2(0x10094): [c3t0] setupTraps+4(0x10096): [c0t0] initMemory+26(0x10156): [c0t0] initMemory+30(0x1015a): [c0t0] initMemory+32(0x1015c): [c0t0] initMemory+34(0x1015e): [c1t0] setupTraps(0x10092): [c1t0] setupTraps+2(0x10094): [c1t0] setupTraps+4(0x10096): [c2t0] setupTraps(0x10092): [c2t0] setupTraps+2(0x10094): [c2t0] setupTraps+4(0x10096): [c2t0] _start+16(0x10ad4): [c3t0] _start+16(0x10ad4): [c0t0] initMemory+26(0x10156): [c0t0] initMemory+30(0x1015a): [c0t0] initMemory+32(0x1015c): [c0t0] initMemory+34(0x1015e): [c0t0] initMemory+36(0x10160): [c1t0] _start+16(0x10ad4): [c1t0] resetChanends(0x100a0): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] resetChanends(0x100a4): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c0t0] initMemory+24(0x10154): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c0t0] _start+8(0x10af2): [c0t0] initPointers(0x10048): [c0t0] initPointers+4(0x1004c): [c0t0] initPointers+6(0x1004e): [c0t0] initPointers+10(0x10052): [c0t0] initPointers+12(0x10054): [c0t0] initPointers+14(0x10056): [c0t0] initPointers+18(0x1005a): [c0t0] initPointers+22(0x1005e): [c0t0] initPointers+26(0x10062): [c0t0] initPointers+28(0x10064): [c0t0] initPointers+30(0x10066): [c0t0] initPointers+32(0x10068): [c0t0] initPointers+34(0x1006a): [c0t0] initPointers+36(0x1006c): [c0t0] initPointers+40(0x10070): [c0t0] initPointers+42(0x10072): [c0t0] initPointers+44(0x10074): [c0t0] initPointers+48(0x10078): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c0t0] _start+12(0x10af6): [c0t0] setupTraps(0x10092): [c0t0] setupTraps+2(0x10094): [c0t0] setupTraps+4(0x10096): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c0t0] _start+16(0x10afa): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c0t0] resetChanends(0x100a0): [c0t0] resetChanends+2(0x100a2): [c0t0] resetChanends+4(0x100a4): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c0t0] resetChanends+2(0x100a2): [c0t0] resetChanends+4(0x100a4): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c0t0] resetChanends+2(0x100a2): [c0t0] resetChanends+4(0x100a4): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c0t0] resetChanends+2(0x100a2): [c0t0] resetChanends+4(0x100a4): [c0t0] resetChanends+2(0x100a2): [c0t0] resetChanends+4(0x100a4): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c0t0] resetChanends+2(0x100a2): [c0t0] resetChanends+4(0x100a4): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] resetChanends+2(0x100a6): [c3t0] resetChanends+4(0x100a8): [c0t0] resetChanends+2(0x100a2): [c0t0] resetChanends+4(0x100a4): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c1t0] resetChanends+2(0x100a2): [c1t0] resetChanends+4(0x100a4): [c2t0] resetChanends+2(0x100a6): [c2t0] resetChanends+4(0x100a8): [c3t0] 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resetChanends+24(0x100b8): [c1t0] resetChanends+26(0x100ba): [c1t0] resetChanends+28(0x100bc): [c0t0] resetChanends+20(0x100b4): [c0t0] resetChanends+22(0x100b6): [c0t0] resetChanends+24(0x100b8): [c0t0] resetChanends+26(0x100ba): [c0t0] resetChanends+28(0x100bc): [c2t0] resetChanends+20(0x100b8): [c2t0] resetChanends+22(0x100ba): [c2t0] resetChanends+24(0x100bc): [c2t0] resetChanends+26(0x100be): [c2t0] resetChanends+28(0x100c0): [c3t0] resetChanends+20(0x100b8): [c3t0] resetChanends+22(0x100ba): [c3t0] resetChanends+24(0x100bc): [c3t0] resetChanends+26(0x100be): [c3t0] resetChanends+28(0x100c0): [c1t0] resetChanends+20(0x100b4): [c1t0] resetChanends+22(0x100b6): [c1t0] resetChanends+24(0x100b8): [c1t0] resetChanends+26(0x100ba): [c1t0] resetChanends+28(0x100bc): [c0t0] resetChanends+20(0x100b4): [c0t0] resetChanends+22(0x100b6): [c0t0] resetChanends+24(0x100b8): [c0t0] resetChanends+26(0x100ba): [c0t0] resetChanends+28(0x100bc): [c2t0] resetChanends+20(0x100b8): [c2t0] resetChanends+22(0x100ba): [c2t0] resetChanends+24(0x100bc): [c2t0] resetChanends+26(0x100be): [c2t0] resetChanends+28(0x100c0): [c3t0] resetChanends+20(0x100b8): [c3t0] resetChanends+22(0x100ba): [c3t0] resetChanends+24(0x100bc): [c3t0] resetChanends+26(0x100be): [c3t0] resetChanends+28(0x100c0): [c1t0] resetChanends+20(0x100b4): [c1t0] resetChanends+22(0x100b6): [c1t0] resetChanends+24(0x100b8): [c1t0] resetChanends+26(0x100ba): [c1t0] resetChanends+28(0x100bc): [c0t0] resetChanends+20(0x100b4): [c0t0] resetChanends+22(0x100b6): [c0t0] resetChanends+24(0x100b8): [c0t0] resetChanends+26(0x100ba): [c0t0] resetChanends+28(0x100bc): [c2t0] resetChanends+20(0x100b8): [c2t0] resetChanends+22(0x100ba): [c2t0] res bl -1338 # lr=0x10aee bl -1319 # lr=0x10ac8 bl -1319 # lr=0x10ac8 bl -1319 # lr=0x10ac8 ldc r0, 0 # r0=0x0 ldc r1, 0 # r1=0x0 ldc r2, 0 # r2=0x0 ldc r3, 0 # r3=0x0 ldc r4, 0 # r4=0x0 ldc r5, 0 # r5=0x0 ldc r6, 0 # r6=0x0 ldc r7, 0 # r7=0x0 ldc r8, 0 # r8=0x0 ldc r9, 0 # r9=0x0 ldc r10, 0 # r10=0x0 retsp 0 # sp=0x0, lr=0x10ac8 ldc r0, 0 # r0=0x0 ldc r1, 0 # r1=0x0 ldc r2, 0 # r2=0x0 ldc r3, 0 # r3=0x0 ldc r4, 0 # r4=0x0 ldc r5, 0 # r5=0x0 ldc r6, 0 # r6=0x0 ldc r7, 0 # r7=0x0 ldc r8, 0 # r8=0x0 ldc r9, 0 # r9=0x0 ldc r10, 0 # r10=0x0 retsp 0 # sp=0x0, lr=0x10aee ldc r0, 0 # r0=0x0 ldc r1, 0 # r1=0x0 ldc r2, 0 # r2=0x0 ldc r3, 0 # r3=0x0 ldc r4, 0 # r4=0x0 ldc r5, 0 # r5=0x0 ldc r6, 0 # r6=0x0 ldc r7, 0 # r7=0x0 ldc r8, 0 # r8=0x0 ldc r9, 0 # r9=0x0 ldc r10, 0 # r10=0x0 retsp 0 # sp=0x0, lr=0x10ac8 ldc r0, 0 # r0=0x0 ldc r1, 0 # r1=0x0 ldc r2, 0 # r2=0x0 ldc r3, 0 # r3=0x0 ldc r4, 0 # r4=0x0 ldc r5, 0 # r5=0x0 ldc r6, 0 # r6=0x0 ldc r7, 0 # r7=0x0 ldc r8, 0 # r8=0x0 ldc r9, 0 # r9=0x0 ldc r10, 0 # r10=0x0 retsp 0 # sp=0x0, lr=0x10ac8 bl -1222 # lr=0x10acc bl -1222 # lr=0x10acc bl -1243 # lr=0x10af2 bl -1224 # lr=0x10acc ldap r11, 1698 # r11=0x10e84 mov r2, r11(0x10e84) # r2=0x10e84 ldap r11, 1701 # r11=0x10e90 mov r0, r11(0x10e90) # r0=0x10e90 sub r0, r0(0x10e90), r2(0x10e84) # r0=0xc shr r3, r0(0xc), 2 # r3=0x3 ldc r0, 0 # r0=0x0 mov r1, r0(0x0) # r1=0x0 lss r11, r0(0x0), r3(0x3) # r11=0x1 bt r11(0x1), 1 stw r0(0x0), r2(0x10e84)[r1(0x0)] add r1, r1(0x0), 1 # r1=0x1 lss r11, r1(0x1), r3(0x3) # r11=0x1 bt r11(0x1), -5 ldap r11, 1696 # r11=0x10e84 mov r2, r11(0x10e84) # r2=0x10e84 ldap r11, 1699 # r11=0x10e90 mov r0, r11(0x10e90) # r0=0x10e90 sub r0, r0(0x10e90), r2(0x10e84) # r0=0xc shr r3, r0(0xc), 2 # r3=0x3 ldc r0, 0 # r0=0x0 mov r1, r0(0x0) # r1=0x0 lss r11, r0(0x0), r3(0x3) # r11=0x1 bt r11(0x1), 1 stw r0(0x0), r2(0x10e84)[r1(0x0)] add r1, r1(0x0), 1 # r1=0x1 lss r11, r1(0x1), r3(0x3) # r11=0x1 bt r11(0x1), -5 ldap r11, 1696 # r11=0x10e84 mov r2, r11(0x10e84) # r2=0x10e84 ldap r11, 1699 # r11=0x10e90 mov r0, r11(0x10e90) # r0=0x10e90 sub r0, r0(0x10e90), r2(0x10e84) # r0=0xc shr r3, r0(0xc), 2 # r3=0x3 ldc r0, 0 # r0=0x0 mov r1, r0(0x0) # r1=0x0 lss r11, r0(0x0), r3(0x3) # r11=0x1 bt r11(0x1), 1 stw r0(0x0), r2(0x10e84)[r1(0x0)] add r1, r1(0x0), 1 # r1=0x1 lss r11, r1(0x1), r3(0x3) # r11=0x1 bt r11(0x1), -5 ldap r11, 1966 # r11=0x1109c mov r2, r11(0x1109c) # r2=0x1109c ldap r11, 1985 # r11=0x110c8 mov r0, r11(0x110c8) # r0=0x110c8 sub r0, r0(0x110c8), r2(0x1109c) # r0=0x2c shr r3, r0(0x2c), 2 # r3=0xb ldc r0, 0 # r0=0x0 mov r1, r0(0x0) # r1=0x0 lss r11, r0(0x0), r3(0xb) # r11=0x1 bt r11(0x1), 1 stw r0(0x0), r2(0x1109c)[r1(0x0)] add r1, r1(0x0), 1 # r1=0x1 lss r11, r1(0x1), r3(0xb) # r11=0x1 bt r11(0x1), -5 stw r0(0x0), r2(0x1109c)[r1(0x1)] add r1, r1(0x1), 1 # r1=0x2 lss r11, r1(0x2), r3(0xb) # r11=0x1 bt r11(0x1), -5 stw r0(0x0), r2(0x10e84)[r1(0x1)] add r1, r1(0x1), 1 # r1=0x2 lss r11, r1(0x2), r3(0x3) # r11=0x1 bt r11(0x1), -5 stw r0(0x0), r2(0x10e84)[r1(0x1)] add r1, r1(0x1), 1 # r1=0x2 lss r11, r1(0x2), r3(0x3) # r11=0x1 bt r11(0x1), -5 stw r0(0x0), r2(0x10e84)[r1(0x1)] add r1, r1(0x1), 1 # r1=0x2 lss r11, r1(0x2), r3(0x3) # r11=0x1 bt r11(0x1), -5 stw r0(0x0), r2(0x10e84)[r1(0x2)] add r1, r1(0x2), 1 # r1=0x3 lss r11, r1(0x3), r3(0x3) # r11=0x0 bt r11(0x0), -5 bu -7 stw r0(0x0), r2(0x1109c)[r1(0x2)] add r1, r1(0x2), 1 # r1=0x3 lss r11, r1(0x3), r3(0xb) # r11=0x1 bt r11(0x1), -5 stw r0(0x0), r2(0x10e84)[r1(0x2)] add r1, r1(0x2), 1 # r1=0x3 lss r11, r1(0x3), r3(0x3) # r11=0x0 bt r11(0x0), -5 bu -7 stw r0(0x0), r2(0x10e84)[r1(0x2)] add r1, r1(0x2), 1 # r1=0x3 lss r11, r1(0x3), r3(0x3) # r11=0x0 bt r11(0x0), -5 bu -7 stw r0(0x0), r2(0x1109c)[r1(0x3)] add r1, r1(0x3), 1 # r1=0x4 lss r11, r1(0x4), r3(0xb) # r11=0x1 bt r11(0x1), -5 retsp 0 # sp=0x0, lr=0x10acc retsp 0 # sp=0x0, lr=0x10acc retsp 0 # sp=0x0, lr=0x10acc bl -1348 # lr=0x10ad0 bl -1348 # lr=0x10ad0 bl -1348 # lr=0x10ad0 ldap r11, 1578 # r11=0x10ca0 set cp, r11(0x10ca0) # cp=0x10ca0 ldap r11, 1633 # r11=0x10d14 set dp, r11(0x10d14) # dp=0x10d14 ldc r11, 11 # r11=0xb ldc r10, 267 # r10=0x10b get r9, ps[r11(0xb)] # r9=0x10000 set r9(0x10000), ps[r10(0x10b)] shl r11, r9(0x10000), 1 # r11=0x20000 sub r11, r11(0x20000), 8 # r11=0x1fff8 set sp, r11(0x1fff8) # sp=0x1fff8 stw r11(0x1fff8), sp[0] krestsp 0 # sp=0x1fff8, ksp=0x1fff8 ldc r10, 512 # r10=0x200 sub r11, r11(0x1fff8), r10(0x200) # r11=0x1fdf8 set sp, r11(0x1fdf8) # sp=0x1fdf8 stw r11(0x1fdf8), dp[_sp(0x10d78)] retsp 0 # sp=0x1fdf8, lr=0x10ad0 stw r0(0x0), r2(0x1109c)[r1(0x4)] add r1, r1(0x4), 1 # r1=0x5 lss r11, r1(0x5), r3(0xb) # r11=0x1 bt r11(0x1), -5 ldap r11, 1578 # r11=0x10ca0 set cp, r11(0x10ca0) # cp=0x10ca0 ldap r11, 1633 # r11=0x10d14 set dp, r11(0x10d14) # dp=0x10d14 ldc r11, 11 # r11=0xb ldc r10, 267 # r10=0x10b get r9, ps[r11(0xb)] # r9=0x10000 set r9(0x10000), ps[r10(0x10b)] shl r11, r9(0x10000), 1 # r11=0x20000 sub r11, r11(0x20000), 8 # r11=0x1fff8 set sp, r11(0x1fff8) # sp=0x1fff8 stw r11(0x1fff8), sp[0] krestsp 0 # sp=0x1fff8, ksp=0x1fff8 ldc r10, 512 # r10=0x200 sub r11, r11(0x1fff8), r10(0x200) # r11=0x1fdf8 set sp, r11(0x1fdf8) # sp=0x1fdf8 stw r11(0x1fdf8), dp[_sp(0x10d78)] retsp 0 # sp=0x1fdf8, lr=0x10ad0 ldap r11, 1578 # r11=0x10ca0 set cp, r11(0x10ca0) # cp=0x10ca0 ldap r11, 1633 # r11=0x10d14 set dp, r11(0x10d14) # dp=0x10d14 ldc r11, 11 # r11=0xb ldc r10, 267 # r10=0x10b get r9, ps[r11(0xb)] # r9=0x10000 set r9(0x10000), ps[r10(0x10b)] shl r11, r9(0x10000), 1 # r11=0x20000 sub r11, r11(0x20000), 8 # r11=0x1fff8 set sp, r11(0x1fff8) # sp=0x1fff8 stw r11(0x1fff8), sp[0] krestsp 0 # sp=0x1fff8, ksp=0x1fff8 ldc r10, 512 # r10=0x200 sub r11, r11(0x1fff8), r10(0x200) # r11=0x1fdf8 set sp, r11(0x1fdf8) # sp=0x1fdf8 stw r11(0x1fdf8), dp[_sp(0x10d78)] retsp 0 # sp=0x1fdf8, lr=0x10ad0 stw r0(0x0), r2(0x1109c)[r1(0x5)] add r1, r1(0x5), 1 # r1=0x6 lss r11, r1(0x6), r3(0xb) # r11=0x1 bt r11(0x1), -5 stw r0(0x0), r2(0x1109c)[r1(0x6)] add r1, r1(0x6), 1 # r1=0x7 lss r11, r1(0x7), r3(0xb) # r11=0x1 bt r11(0x1), -5 stw r0(0x0), r2(0x1109c)[r1(0x7)] add r1, r1(0x7), 1 # r1=0x8 lss r11, r1(0x8), r3(0xb) # r11=0x1 bt r11(0x1), -5 stw r0(0x0), r2(0x1109c)[r1(0x8)] add r1, r1(0x8), 1 # r1=0x9 lss r11, r1(0x9), r3(0xb) # r11=0x1 bt r11(0x1), -5 bl -1313 # lr=0x10ad4 bl -1313 # lr=0x10ad4 bl -1313 # lr=0x10ad4 ldap r11, -74 # r11=0x10000 set kep, r11(0x10000) # kep=0x10000 retsp 0 # sp=0x1fdf8, lr=0x10ad4 stw r0(0x0), r2(0x1109c)[r1(0x9)] add r1, r1(0x9), 1 # r1=0xa lss r11, r1(0xa), r3(0xb) # r11=0x1 bt r11(0x1), -5 ldap r11, -74 # r11=0x10000 set kep, r11(0x10000) # kep=0x10000 retsp 0 # sp=0x1fdf8, lr=0x10ad4 ldap r11, -74 # r11=0x10000 set kep, r11(0x10000) # kep=0x10000 retsp 0 # sp=0x1fdf8, lr=0x10ad4 bl -1306 # lr=0x10ad8 bl -1306 # lr=0x10ad8 stw r0(0x0), r2(0x1109c)[r1(0xa)] add r1, r1(0xa), 1 # r1=0xb lss r11, r1(0xb), r3(0xb) # r11=0x0 bt r11(0x0), -5 bu -7 bl -1308 # lr=0x10ad8 getr r1, 2 # r1=0x10002 getr r0, 2 # r0=0x10102 bt r0(0x10102), -2 getr r1, 2 # r1=0x20002 getr r0, 2 # r0=0x20102 bt r0(0x20102), -2 getr r1, 2 # r1=0x30002 getr r0, 2 # r0=0x30102 bt r0(0x30102), -2 getr r0, 2 # r0=0x30202 bt r0(0x30202), -2 getr r0, 2 # r0=0x10202 bt r0(0x10202), -2 getr r0, 2 # r0=0x20202 bt r0(0x20202), -2 retsp 0 # sp=0x0, lr=0x10af2 getr r0, 2 # r0=0x30302 bt r0(0x30302), -2 getr r0, 2 # r0=0x10302 bt r0(0x10302), -2 getr r0, 2 # r0=0x20302 bt r0(0x20302), -2 bl -1367 # lr=0x10af6 ldap r11, 1834 # r11=0x10ea0 set cp, r11(0x10ea0) # cp=0x10ea0 ldap r11, 1901 # r11=0x10f2c set dp, r11(0x10f2c) # dp=0x10f2c ldc r11, 11 # r11=0xb ldc r10, 267 # r10=0x10b get r9, ps[r11(0xb)] # r9=0x10000 set r9(0x10000), ps[r10(0x10b)] shl r11, r9(0x10000), 1 # r11=0x20000 sub r11, r11(0x20000), 8 # r11=0x1fff8 set sp, r11(0x1fff8) # sp=0x1fff8 stw r11(0x1fff8), sp[0] krestsp 0 # sp=0x1fff8, ksp=0x1fff8 ldc r10, 512 # r10=0x200 sub r11, r11(0x1fff8), r10(0x200) # r11=0x1fdf8 set sp, r11(0x1fdf8) # sp=0x1fdf8 stw r11(0x1fdf8), dp[_sp(0x10f90)] retsp 0 # sp=0x1fdf8, lr=0x10af6 getr r0, 2 # r0=0x30402 bt r0(0x30402), -2 getr r0, 2 # r0=0x10402 bt r0(0x10402), -2 getr r0, 2 # r0=0x20402 bt r0(0x20402), -2 getr r0, 2 # r0=0x20502 bt r0(0x20502), -2 getr r0, 2 # r0=0x30502 bt r0(0x30502), -2 getr r0, 2 # r0=0x10502 bt r0(0x10502), -2 getr r0, 2 # r0=0x10602 bt r0(0x10602), -2 getr r0, 2 # r0=0x20602 bt r0(0x20602), -2 getr r0, 2 # r0=0x30602 bt r0(0x30602), -2 getr r0, 2 # r0=0x30702 bt r0(0x30702), -2 getr r0, 2 # r0=0x10702 bt r0(0x10702), -2 getr r0, 2 # r0=0x20702 bt r0(0x20702), -2 getr r0, 2 # r0=0x20802 bt r0(0x20802), -2 getr r0, 2 # r0=0x30802 bt r0(0x30802), -2 getr r0, 2 # r0=0x10802 bt r0(0x10802), -2 getr r0, 2 # r0=0x10902 bt r0(0x10902), -2 getr r0, 2 # r0=0x20902 bt r0(0x20902), -2 getr r0, 2 # r0=0x30902 bt r0(0x30902), -2 getr r0, 2 # r0=0x30a02 bt r0(0x30a02), -2 getr r0, 2 # r0=0x10a02 bt r0(0x10a02), -2 getr r0, 2 # r0=0x20a02 bt r0(0x20a02), -2 getr r0, 2 # r0=0x20b02 bt r0(0x20b02), -2 getr r0, 2 # r0=0x30b02 bt r0(0x30b02), -2 getr r0, 2 # r0=0x10b02 bt r0(0x10b02), -2 getr r0, 2 # r0=0x10c02 bt r0(0x10c02), -2 getr r0, 2 # r0=0x20c02 bt r0(0x20c02), -2 getr r0, 2 # r0=0x30c02 bt r0(0x30c02), -2 getr r0, 2 # r0=0x30d02 bt r0(0x30d02), -2 getr r0, 2 # r0=0x10d02 bt r0(0x10d02), -2 getr r0, 2 # r0=0x20d02 bt r0(0x20d02), -2 bl -1332 # lr=0x10afa ldap r11, -74 # r11=0x10000 set kep, r11(0x10000) # kep=0x10000 retsp 0 # sp=0x1fdf8, lr=0x10afa getr r0, 2 # r0=0x30e02 bt r0(0x30e02), -2 getr r0, 2 # r0=0x10e02 bt r0(0x10e02), -2 getr r0, 2 # r0=0x20e02 bt r0(0x20e02), -2 getr r0, 2 # r0=0x20f02 bt r0(0x20f02), -2 getr r0, 2 # r0=0x30f02 bt r0(0x30f02), -2 getr r0, 2 # r0=0x10f02 bt r0(0x10f02), -2 getr r0, 2 # r0=0x11002 bt r0(0x11002), -2 bl -1327 # lr=0x10afe getr r0, 2 # r0=0x21002 bt r0(0x21002), -2 getr r0, 2 # r0=0x31002 bt r0(0x31002), -2 getr r1, 2 # r1=0x2 getr r0, 2 # r0=0x102 bt r0(0x102), -2 getr r0, 2 # r0=0x11102 bt r0(0x11102), -2 getr r0, 2 # r0=0x21102 bt r0(0x21102), -2 getr r0, 2 # r0=0x31102 bt r0(0x31102), -2 getr r0, 2 # r0=0x31202 bt r0(0x31202), -2 getr r0, 2 # r0=0x202 bt r0(0x202), -2 getr r0, 2 # r0=0x11202 bt r0(0x11202), -2 getr r0, 2 # r0=0x21202 bt r0(0x21202), -2 getr r0, 2 # r0=0x21302 bt r0(0x21302), -2 getr r0, 2 # r0=0x31302 bt r0(0x31302), -2 getr r0, 2 # r0=0x302 bt r0(0x302), -2 getr r0, 2 # r0=0x11302 bt r0(0x11302), -2 getr r0, 2 # r0=0x11402 bt r0(0x11402), -2 getr r0, 2 # r0=0x21402 bt r0(0x21402), -2 getr r0, 2 # r0=0x31402 bt r0(0x31402), -2 getr r0, 2 # r0=0x402 bt r0(0x402), -2 getr r0, 2 # r0=0x502 bt r0(0x502), -2 getr r0, 2 # r0=0x11502 bt r0(0x11502), -2 getr r0, 2 # r0=0x21502 bt r0(0x21502), -2 getr r0, 2 # r0=0x31502 bt r0(0x31502), -2 getr r0, 2 # r0=0x31602 bt r0(0x31602), -2 getr r0, 2 # r0=0x602 bt r0(0x602), -2 getr r0, 2 # r0=0x11602 bt r0(0x11602), -2 getr r0, 2 # r0=0x21602 bt r0(0x21602), -2 getr r0, 2 # r0=0x21702 bt r0(0x21702), -2 getr r0, 2 # r0=0x31702 bt r0(0x31702), -2 getr r0, 2 # r0=0x702 bt r0(0x702), -2 getr r0, 2 # r0=0x11702 bt r0(0x11702), -2 getr r0, 2 # r0=0x11802 bt r0(0x11802), -2 getr r0, 2 # r0=0x21802 bt r0(0x21802), -2 getr r0, 2 # r0=0x31802 bt r0(0x31802), -2 getr r0, 2 # r0=0x802 bt r0(0x802), -2 getr r0, 2 # r0=0x902 bt r0(0x902), -2 getr r0, 2 # r0=0x11902 bt r0(0x11902), -2 getr r0, 2 # r0=0x21902 bt r0(0x21902), -2 getr r0, 2 # r0=0x31902 bt r0(0x31902), -2 getr r0, 2 # r0=0x31a02 bt r0(0x31a02), -2 getr r0, 2 # r0=0xa02 bt r0(0xa02), -2 getr r0, 2 # r0=0x11a02 bt r0(0x11a02), -2 getr r0, 2 # r0=0x21a02 bt r0(0x21a02), -2 getr r0, 2 # r0=0x21b02 bt r0(0x21b02), -2 getr r0, 2 # r0=0x31b02 bt r0(0x31b02), -2 getr r0, 2 # r0=0xb02 bt r0(0xb02), -2 getr r0, 2 # r0=0x11b02 bt r0(0x11b02), -2 getr r0, 2 # r0=0x11c02 bt r0(0x11c02), -2 getr r0, 2 # r0=0x21c02 bt r0(0x21c02), -2 getr r0, 2 # r0=0x31c02 bt r0(0x31c02), -2 getr r0, 2 # r0=0xc02 bt r0(0xc02), -2 getr r0, 2 # r0=0xd02 bt r0(0xd02), -2 getr r0, 2 # r0=0x11d02 bt r0(0x11d02), -2 getr r0, 2 # r0=0x21d02 bt r0(0x21d02), -2 getr r0, 2 # r0=0x31d02 bt r0(0x31d02), -2 getr r0, 2 # r0=0x31e02 bt r0(0x31e02), -2 getr r0, 2 # r0=0xe02 bt r0(0xe02), -2 getr r0, 2 # r0=0x11e02 bt r0(0x11e02), -2 getr r0, 2 # r0=0x21e02 bt r0(0x21e02), -2 getr r0, 2 # r0=0x21f02 bt r0(0x21f02), -2 getr r0, 2 # r0=0x31f02 bt r0(0x31f02), -2 getr r0, 2 # r0=0xf02 bt r0(0xf02), -2 getr r0, 2 # r0=0x11f02 bt r0(0x11f02), -2 getr r0, 2 # r0=0x0 bt r0(0x0), -2 ldw r0, cp[.CPM0(0x10d08)] # r0=0xffff00ff and r11, r1(0x10002), r0(0xffff00ff) # r11=0x10002 ldc r3, 0 # r3=0x0 ldc r2, 256 # r2=0x100 ldc r1, 32 # r1=0x20 freer res[r11(0x10002)] add r11, r11(0x10002), r2(0x100) # r11=0x10102 add r3, r3(0x0), 1 # r3=0x1 lss r0, r3(0x1), r1(0x20) # r0=0x1 bt r0(0x1), -5 getr r0, 2 # r0=0x0 bt r0(0x0), -2 ldw r0, cp[.CPM0(0x10d08)] # r0=0xffff00ff and r11, r1(0x20002), r0(0xffff00ff) # r11=0x20002 ldc r3, 0 # r3=0x0 ldc r2, 256 # r2=0x100 ldc r1, 32 # r1=0x20 freer res[r11(0x20002)] add r11, r11(0x20002), r2(0x100) # r11=0x20102 add r3, r3(0x0), 1 # r3=0x1 lss r0, r3(0x1), r1(0x20) # r0=0x1 bt r0(0x1), -5 getr r0, 2 # r0=0x0 bt r0(0x0), -2 ldw r0, cp[.CPM0(0x10d08)] # r0=0xffff00ff and r11, r1(0x30002), r0(0xffff00ff) # r11=0x30002 ldc r3, 0 # r3=0x0 ldc r2, 256 # r2=0x100 ldc r1, 32 # r1=0x20 freer res[r11(0x30002)] add r11, r11(0x30002), r2(0x100) # r11=0x30102 add r3, r3(0x0), 1 # r3=0x1 lss r0, r3(0x1), r1(0x20) # r0=0x1 bt r0(0x1), -5 getr r0, 2 # r0=0x1002 bt r0(0x1002), -2 getr r0, 2 # r0=0x1102 bt r0(0x1102), -2 getr r0, 2 # r0=0x1202 bt r0(0x1202), -2 getr r0, 2 # r0=0x1302 bt r0(0x1302), -2 getr r0, 2 # r0=0x1402 bt r0(0x1402), -2 getr r0, 2 # r0=0x1502 bt r0(0x1502), -2 getr r0, 2 # r0=0x1602 bt r0(0x1602), -2 freer res[r11(0x10102)] add r11, r11(0x10102), r2(0x100) # r11=0x10202 add r3, r3(0x1), 1 # r3=0x2 lss r0, r3(0x2), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x20102)] add r11, r11(0x20102), r2(0x100) # r11=0x20202 add r3, r3(0x1), 1 # r3=0x2 lss r0, r3(0x2), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x30102)] add r11, r11(0x30102), r2(0x100) # r11=0x30202 add r3, r3(0x1), 1 # r3=0x2 lss r0, r3(0x2), r1(0x20) # r0=0x1 bt r0(0x1), -5 getr r0, 2 # r0=0x1702 bt r0(0x1702), -2 getr r0, 2 # r0=0x1802 bt r0(0x1802), -2 freer res[r11(0x10202)] add r11, r11(0x10202), r2(0x100) # r11=0x10302 add r3, r3(0x2), 1 # r3=0x3 lss r0, r3(0x3), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x20202)] add r11, r11(0x20202), r2(0x100) # r11=0x20302 add r3, r3(0x2), 1 # r3=0x3 lss r0, r3(0x3), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x30202)] add r11, r11(0x30202), r2(0x100) # r11=0x30302 add r3, r3(0x2), 1 # r3=0x3 lss r0, r3(0x3), r1(0x20) # r0=0x1 bt r0(0x1), -5 getr r0, 2 # r0=0x1902 bt r0(0x1902), -2 getr r0, 2 # r0=0x1a02 bt r0(0x1a02), -2 getr r0, 2 # r0=0x1b02 bt r0(0x1b02), -2 freer res[r11(0x10302)] add r11, r11(0x10302), r2(0x100) # r11=0x10402 add r3, r3(0x3), 1 # r3=0x4 lss r0, r3(0x4), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x20302)] add r11, r11(0x20302), r2(0x100) # r11=0x20402 add r3, r3(0x3), 1 # r3=0x4 lss r0, r3(0x4), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x30302)] add r11, r11(0x30302), r2(0x100) # r11=0x30402 add r3, r3(0x3), 1 # r3=0x4 lss r0, r3(0x4), r1(0x20) # r0=0x1 bt r0(0x1), -5 getr r0, 2 # r0=0x1c02 bt r0(0x1c02), -2 getr r0, 2 # r0=0x1d02 bt r0(0x1d02), -2 freer res[r11(0x10402)] add r11, r11(0x10402), r2(0x100) # r11=0x10502 add r3, r3(0x4), 1 # r3=0x5 lss r0, r3(0x5), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x20402)] add r11, r11(0x20402), r2(0x100) # r11=0x20502 add r3, r3(0x4), 1 # r3=0x5 lss r0, r3(0x5), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x30402)] add r11, r11(0x30402), r2(0x100) # r11=0x30502 add r3, r3(0x4), 1 # r3=0x5 lss r0, r3(0x5), r1(0x20) # r0=0x1 bt r0(0x1), -5 getr r0, 2 # r0=0x1e02 bt r0(0x1e02), -2 getr r0, 2 # r0=0x1f02 bt r0(0x1f02), -2 getr r0, 2 # r0=0x0 bt r0(0x0), -2 ldw r0, cp[.CPM0(0x10f20)] # r0=0xffff00ff and r11, r1(0x2), r0(0xffff00ff) # r11=0x2 ldc r3, 0 # r3=0x0 ldc r2, 256 # r2=0x100 ldc r1, 32 # r1=0x20 freer res[r11(0x2)] add r11, r11(0x2), r2(0x100) # r11=0x102 add r3, r3(0x0), 1 # r3=0x1 lss r0, r3(0x1), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x10502)] add r11, r11(0x10502), r2(0x100) # r11=0x10602 add r3, r3(0x5), 1 # r3=0x6 lss r0, r3(0x6), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x20502)] add r11, r11(0x20502), r2(0x100) # r11=0x20602 add r3, r3(0x5), 1 # r3=0x6 lss r0, r3(0x6), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x30502)] add r11, r11(0x30502), r2(0x100) # r11=0x30602 add r3, r3(0x5), 1 # r3=0x6 lss r0, r3(0x6), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x30602)] add r11, r11(0x30602), r2(0x100) # r11=0x30702 add r3, r3(0x6), 1 # r3=0x7 lss r0, r3(0x7), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x10602)] add r11, r11(0x10602), r2(0x100) # r11=0x10702 add r3, r3(0x6), 1 # r3=0x7 lss r0, r3(0x7), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x20602)] add r11, r11(0x20602), r2(0x100) # r11=0x20702 add r3, r3(0x6), 1 # r3=0x7 lss r0, r3(0x7), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x20702)] add r11, r11(0x20702), r2(0x100) # r11=0x20802 add r3, r3(0x7), 1 # r3=0x8 lss r0, r3(0x8), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x30702)] add r11, r11(0x30702), r2(0x100) # r11=0x30802 add r3, r3(0x7), 1 # r3=0x8 lss r0, r3(0x8), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x10702)] add r11, r11(0x10702), r2(0x100) # r11=0x10802 add r3, r3(0x7), 1 # r3=0x8 lss r0, r3(0x8), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x102)] add r11, r11(0x102), r2(0x100) # r11=0x202 add r3, r3(0x1), 1 # r3=0x2 lss r0, r3(0x2), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x20802)] add r11, r11(0x20802), r2(0x100) # r11=0x20902 add r3, r3(0x8), 1 # r3=0x9 lss r0, r3(0x9), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x30802)] add r11, r11(0x30802), r2(0x100) # r11=0x30902 add r3, r3(0x8), 1 # r3=0x9 lss r0, r3(0x9), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x10802)] add r11, r11(0x10802), r2(0x100) # r11=0x10902 add r3, r3(0x8), 1 # r3=0x9 lss r0, r3(0x9), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x202)] add r11, r11(0x202), r2(0x100) # r11=0x302 add r3, r3(0x2), 1 # r3=0x3 lss r0, r3(0x3), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x20902)] add r11, r11(0x20902), r2(0x100) # r11=0x20a02 add r3, r3(0x9), 1 # r3=0xa lss r0, r3(0xa), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x30902)] add r11, r11(0x30902), r2(0x100) # r11=0x30a02 add r3, r3(0x9), 1 # r3=0xa lss r0, r3(0xa), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x10902)] add r11, r11(0x10902), r2(0x100) # r11=0x10a02 add r3, r3(0x9), 1 # r3=0xa lss r0, r3(0xa), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x302)] add r11, r11(0x302), r2(0x100) # r11=0x402 add r3, r3(0x3), 1 # r3=0x4 lss r0, r3(0x4), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x20a02)] add r11, r11(0x20a02), r2(0x100) # r11=0x20b02 add r3, r3(0xa), 1 # r3=0xb lss r0, r3(0xb), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x30a02)] add r11, r11(0x30a02), r2(0x100) # r11=0x30b02 add r3, r3(0xa), 1 # r3=0xb lss r0, r3(0xb), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x10a02)] add r11, r11(0x10a02), r2(0x100) # r11=0x10b02 add r3, r3(0xa), 1 # r3=0xb lss r0, r3(0xb), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x402)] add r11, r11(0x402), r2(0x100) # r11=0x502 add r3, r3(0x4), 1 # r3=0x5 lss r0, r3(0x5), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x20b02)] add r11, r11(0x20b02), r2(0x100) # r11=0x20c02 add r3, r3(0xb), 1 # r3=0xc lss r0, r3(0xc), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x30b02)] add r11, r11(0x30b02), r2(0x100) # r11=0x30c02 add r3, r3(0xb), 1 # r3=0xc lss r0, r3(0xc), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x10b02)] add r11, r11(0x10b02), r2(0x100) # r11=0x10c02 add r3, r3(0xb), 1 # r3=0xc lss r0, r3(0xc), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x502)] add r11, r11(0x502), r2(0x100) # r11=0x602 add r3, r3(0x5), 1 # r3=0x6 lss r0, r3(0x6), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x20c02)] add r11, r11(0x20c02), r2(0x100) # r11=0x20d02 add r3, r3(0xc), 1 # r3=0xd lss r0, r3(0xd), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x30c02)] add r11, r11(0x30c02), r2(0x100) # r11=0x30d02 add r3, r3(0xc), 1 # r3=0xd lss r0, r3(0xd), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x10c02)] add r11, r11(0x10c02), r2(0x100) # r11=0x10d02 add r3, r3(0xc), 1 # r3=0xd lss r0, r3(0xd), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x602)] add r11, r11(0x602), r2(0x100) # r11=0x702 add r3, r3(0x6), 1 # r3=0x7 lss r0, r3(0x7), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x20d02)] add r11, r11(0x20d02), r2(0x100) # r11=0x20e02 add r3, r3(0xd), 1 # r3=0xe lss r0, r3(0xe), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x30d02)] add r11, r11(0x30d02), r2(0x100) # r11=0x30e02 add r3, r3(0xd), 1 # r3=0xe lss r0, r3(0xe), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x10d02)] add r11, r11(0x10d02), r2(0x100) # r11=0x10e02 add r3, r3(0xd), 1 # r3=0xe lss r0, r3(0xe), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x702)] add r11, r11(0x702), r2(0x100) # r11=0x802 add r3, r3(0x7), 1 # r3=0x8 lss r0, r3(0x8), r1(0x20) # r0=0x1 bt r0(0x1), -5 freer res[r11(0x20e02)] add r11, r11(0x20e02), r2(0x100) # r11=0x20f02

rlsosborne commented 13 years ago

I couldn't recreate this. I did get a valgrind error running the test which I've fixed in 9acde342f46ea2ccf379dcb666dc9e7cfa7e1ca6, hopefully this was the problem. Could you let me know if it works for you now.

jameshanlon commented 13 years ago

EDIT: sorry this was my fault, I didn't do "git merge upstream/master". Seem to be working fine now.

No, it doesn't seem to have fixed it. Attached below is the last part of the trace which was cropped from my previous comment. It seems to happen only when an event is raised on channel end 0 on core 3, and not on other cores. If I change the on_basic.sire test from

proc main() is var a; { on NUM_CORES-1 do a := 0xDEADBEEF ; printhexln(a) }

to

proc main() is var a; { on NUM_CORES-2 do a := 0xDEADBEEF ; printhexln(a) }

It runs fine. I've emailed you the binary that causes this for me.

[c0t0] _start+46(0x10b18): bl -56 # lr=0x10b1c [c0t0] initMain(0x10aac): getr r1, 4 # r1=0x104 [c0t0] initMain+2(0x10aae): bt r1(0x104), 21 [c0t0] initMain+4(0x10ab0): ldap r11, 114 # r11=0x10b98 [c0t0] initMain+8(0x10ab4): init t[r1(0x104)]:pc, r11(0x10b98) [c0t0] initMain+10(0x10ab6): ldap r11, 20 # r11=0x10ae0 [c0t0] initMain+12(0x10ab8): init t[r1(0x104)]:lr, r11(0x10ae0) [c0t0] initMain+16(0x10abc): ldc r0, 0 # r0=0x0 [c0t0] initMain+18(0x10abe): set t[r1(0x104)]:r0, r0(0x0) [c0t0] initMain+20(0x10ac0): set t[r1(0x104)]:r1, r0(0x0) [c0t0] initMain+22(0x10ac2): set t[r1(0x104)]:r2, r0(0x0) [c0t0] initMain+24(0x10ac4): set t[r1(0x104)]:r3, r0(0x0) [c0t0] initMain+26(0x10ac6): set t[r1(0x104)]:r4, r0(0x0) [c0t0] initMain+28(0x10ac8): set t[r1(0x104)]:r5, r0(0x0) [c0t0] initMain+30(0x10aca): set t[r1(0x104)]:r6, r0(0x0) [c0t0] initMain+32(0x10acc): set t[r1(0x104)]:r7, r0(0x0) [c0t0] initMain+34(0x10ace): set t[r1(0x104)]:r8, r0(0x0) [c0t0] initMain+36(0x10ad0): set t[r1(0x104)]:r9, r0(0x0) [c0t0] initMain+38(0x10ad2): set t[r1(0x104)]:r10, r0(0x0) [c0t0] initMain+40(0x10ad4): set t[r1(0x104)]:r11, r0(0x0) [c0t0] initMain+42(0x10ad6): start t[r1(0x104)] [c0t0] initMain+44(0x10ad8): retsp 0 # sp=0x1fdf8, lr=0x10b1c [c0t1] ._p0.bottom(0x10b98): entsp 7 # sp=0x1f9dc [c0t1] ._p0.bottom+2(0x10b9a): bla cp[1] # lr=0x10b9c [c0t1] _procId(0x10198): getr r2, 2 # r2=0xa02 [c0t1] _procId+2(0x1019a): bitrev r1, r2(0xa02) # r1=0x40500000 [c0t1] _procId+6(0x1019e): mkmsk r0, 8 # r0=0xff [c0t1] _procId+8(0x101a0): and r1, r1(0x40500000), r0(0xff) # r1=0x0 [c0t1] _procId+10(0x101a2): shl r3, r1(0x0), 2 # r3=0x0 [c0t1] _procId+12(0x101a4): shr r1, r2(0xa02), 16 # r1=0x0 [c0t1] _procId+14(0x101a6): and r0, r1(0x0), r0(0xff) # r0=0x0 [c0t1] _procId+16(0x101a8): add r0, r3(0x0), r0(0x0) # r0=0x0 [c0t1] _procId+18(0x101aa): freer res[r2(0xa02)] [c0t1] _procId+20(0x101ac): retsp 0 # sp=0x1f9dc, lr=0x10b9c [c0t1] ._p0.bottom+4(0x10b9c): eq r0, r0(0x0), 3 # r0=0x0 [c0t1] ._p0.bottom+6(0x10b9e): bt r0(0x0), 18 [c0t1] ._p0.bottom+8(0x10ba0): ldaw r1, sp[2] # r1=0x1f9e4 [c0t1] ._p0.bottom+10(0x10ba2): mkmsk r0, 1 # r0=0x1 [c0t1] ._p0.bottom+12(0x10ba4): stw r0(0x1), r1(0x1f9e4)[0] [c0t1] ._p0.bottom+14(0x10ba6): stw r0(0x1), r1(0x1f9e4)[1] [c0t1] ._p0.bottom+16(0x10ba8): ldc r0, 2 # r0=0x2 [c0t1] ._p0.bottom+18(0x10baa): stw r0(0x2), r1(0x1f9e4)[2] [c0t1] ._p0.bottom+20(0x10bac): ldaw r0, sp[1] # r0=0x1f9e0 [c0t1] ._p0.bottom+22(0x10bae): mov r0, r0(0x1f9e0) # r0=0x1f9e0 [c0t1] ._p0.bottom+24(0x10bb0): stw r0(0x1f9e0), r1(0x1f9e4)[3] [c0t1] ._p0.bottom+26(0x10bb2): mkmsk r0, 3 # r0=0x7 [c0t1] ._p0.bottom+28(0x10bb4): stw r0(0x7), r1(0x1f9e4)[4] [c0t1] ._p0.bottom+30(0x10bb6): mkmsk r0, 2 # r0=0x3 [c0t1] ._p0.bottom+32(0x10bb8): ldc r2, 5 # r2=0x5 [c0t1] ._p0.bottom+34(0x10bba): bla cp[_cp(0x10ea0)] # lr=0x10bbc [c0t0] _start+50(0x10b1c): bu -1176 [c0t0] controlIdle(0x101f0): clrsr 3 [c0t0] controlIdle+2(0x101f2): ldw r1, dp[spawn_master(0x10f94)] # r1=0x2 [c0t0] controlIdle+6(0x101f6): setc res[r1(0x2)], 2 [c0t0] controlIdle+8(0x101f8): ldw r0, dp[conn_master(0x10fb8)] # r0=0x102 [c0t0] controlIdle+12(0x101fc): setc res[r0(0x102)], 2 [c0t0] controlIdle+14(0x101fe): ldap r11, -255 # r11=0x10004 [c0t0] controlIdle+18(0x10202): setv res[r1(0x2)], r11(0x10004) [c0t0] controlIdle+20(0x10204): ldap r11, -241 # r11=0x10026 [c0t1] _createProcess(0x1021c): entsp 5 # sp=0x1f9c8 [c0t1] _createProcess+2(0x1021e): stw r4(0x0), sp[1] [c0t1] _createProcess+4(0x10220): stw r5(0x0), sp[2] [c0t1] _createProcess+6(0x10222): stw r6(0x0), sp[3] [c0t1] _createProcess+8(0x10224): stw r7(0x0), sp[4] [c0t1] _createProcess+10(0x10226): mov r5, r1(0x1f9e4) # r5=0x1f9e4 [c0t1] _createProcess+12(0x10228): mov r6, r2(0x5) # r6=0x5 [c0t1] _createProcess+14(0x1022a): get r11, id # r11=0x1 [c0t1] _createProcess+16(0x1022c): mov r4, r11(0x1) # r4=0x1 [c0t1] _createProcess+18(0x1022e): ldaw r2, dp[thread_chans(0x10f98)] # r2=0x10f98 [c0t1] _createProcess+22(0x10232): ldc r1, 8 # r1=0x8 [c0t1] _createProcess+24(0x10234): lsu r1, r4(0x1), r1(0x8) # r1=0x1 [c0t1] _createProcess+26(0x10236): ecallf r1(0x1) [c0t1] _createProcess+28(0x10238): ldw r7, r2(0x10f98)[r4(0x1)] # r7=0x302 [c0t1] _createProcess+30(0x1023a): shr r1, r0(0x3), 2 # r1=0x0 [c0t1] _createProcess+32(0x1023c): bitrev r2, r1(0x0) # r2=0x0 [c0t1] _createProcess+36(0x10240): mkmsk r1, 2 # r1=0x3 [c0t1] _createProcess+38(0x10242): and r0, r0(0x3), r1(0x3) # r0=0x3 [c0t1] _createProcess+40(0x10244): shl r0, r0(0x3), 16 # r0=0x30000 [c0t1] _createProcess+42(0x10246): or r1, r2(0x0), r0(0x30000) # r1=0x30000 [c0t1] _createProcess+44(0x10248): ldc r0, 2 # r0=0x2 [c0t1] _createProcess+46(0x1024a): or r1, r1(0x30000), r0(0x2) # r1=0x30002 [c0t1] _createProcess+48(0x1024c): mov r0, r7(0x302) # r0=0x302 [c0t1] _createProcess+50(0x1024e): bl 20 # lr=0x10250 [c0t0] controlIdle+24(0x10208): setv res[r0(0x102)], r11(0x10026) [c0t0] controlIdle+26(0x1020a): waiteu [c0t1] initHostConnection(0x10278): setd res[r0(0x302)], r1(0x30002) [c0t1] initHostConnection+2(0x1027a): out r0(0x302), res[r0(0x302)] [c3t0] Event caused by channel end 0x30002 # ed=0x30002 Segmentation fault

xcore / tool_axe

Segmentation fault on a channel event #4