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xil-se / xildebug_sw

XilDebug is a CMSIS-DAP compliant debugger, UART bridge and power profiler all in one package.
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main: Fix clock configuration #79

Closed kbeckmann closed 6 years ago

kbeckmann commented 6 years ago

Found this issue when running with USE_FULL_ASSERT.

arturo182 commented 6 years ago

What is the issue though?

kbeckmann commented 6 years ago

.PLL.PLLM must be between 1 and 8. having it set to 0 leads to an assert in the hal. having it set to 1 should be fine as it acts as a divider and we just want to pass through.

kbeckmann commented 6 years ago

I guess the .ioc file should be updated with the correct clock config, can do that later.

kbeckmann commented 6 years ago

image