Fixed timing and improved test coverage

[pthedinger]

Note, there is still one outstanding test failure where the XS1 doesn't meet timing.

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TEST SUMMARY

lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs1;stop=stop;impl=non_comb;speed=400] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs1;stop=stop;impl=comb;speed=100] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs1;stop=stop;impl=comb;speed=10] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs1;stop=stop;impl=non_comb;speed=100] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs1;stop=stop;impl=non_comb;speed=10] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs1;stop=no_stop;impl=non_comb;speed=400] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs1;stop=no_stop;impl=comb;speed=100] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs1;stop=no_stop;impl=comb;speed=10] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs1;stop=no_stop;impl=non_comb;speed=100] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs1;stop=no_stop;impl=non_comb;speed=10] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs2;stop=stop;impl=non_comb;speed=400] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs2;stop=stop;impl=comb;speed=100] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs2;stop=stop;impl=comb;speed=10] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs2;stop=stop;impl=non_comb;speed=100] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs2;stop=stop;impl=non_comb;speed=10] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs2;stop=no_stop;impl=non_comb;speed=400] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs2;stop=no_stop;impl=comb;speed=100] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs2;stop=no_stop;impl=comb;speed=10] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs2;stop=no_stop;impl=non_comb;speed=100] PASS lib_i2c::i2c_master_sim_tests::async_basic_test[arch=xs2;stop=no_stop;impl=non_comb;speed=10] PASS lib_i2c::i2c_master_sim_tests::basic_test[speed=400;stop=stop;arch=xs1] PASS lib_i2c::i2c_master_sim_tests::basic_test[speed=100;stop=stop;arch=xs1] PASS lib_i2c::i2c_master_sim_tests::basic_test[speed=10;stop=stop;arch=xs1] PASS lib_i2c::i2c_master_sim_tests::basic_test[speed=400;stop=no_stop;arch=xs1] PASS lib_i2c::i2c_master_sim_tests::basic_test[speed=100;stop=no_stop;arch=xs1] PASS lib_i2c::i2c_master_sim_tests::basic_test[speed=10;stop=no_stop;arch=xs1] PASS lib_i2c::i2c_master_sim_tests::basic_test[speed=400;stop=stop;arch=xs2] PASS lib_i2c::i2c_master_sim_tests::basic_test[speed=100;stop=stop;arch=xs2] PASS lib_i2c::i2c_master_sim_tests::basic_test[speed=10;stop=stop;arch=xs2] PASS lib_i2c::i2c_master_sim_tests::basic_test[speed=400;stop=no_stop;arch=xs2] PASS lib_i2c::i2c_master_sim_tests::basic_test[speed=100;stop=no_stop;arch=xs2] PASS lib_i2c::i2c_master_sim_tests::basic_test[speed=10;stop=no_stop;arch=xs2] PASS lib_i2c::i2c_slave_sim_tests::basic_test[speed=400] PASS lib_i2c::i2c_slave_sim_tests::basic_test[speed=100] PASS lib_i2c::i2c_slave_sim_tests::basic_test[speed=10] PASS lib_i2c::i2c_master_sim_tests::bus_locks[speed=400;arch=xs1] PASS lib_i2c::i2c_master_sim_tests::bus_locks[speed=400;arch=xs2] PASS lib_i2c::i2c_master_sim_tests::async_interference_test[arch=xs1;stop=stop;speed=100] PASS lib_i2c::i2c_master_sim_tests::async_interference_test[arch=xs1;stop=no_stop;speed=100] PASS lib_i2c::i2c_master_sim_tests::async_interference_test[arch=xs2;stop=stop;speed=100] PASS lib_i2c::i2c_master_sim_tests::async_interference_test[arch=xs2;stop=no_stop;speed=100] PASS lib_i2c::i2c_master_sim_tests::ack_test[arch=xs1;stop=stop;speed=400] PASS lib_i2c::i2c_master_sim_tests::ack_test[arch=xs1;stop=no_stop;speed=400] PASS lib_i2c::i2c_master_sim_tests::ack_test[arch=xs2;stop=stop;speed=400] PASS lib_i2c::i2c_master_sim_tests::ack_test[arch=xs2;stop=no_stop;speed=400] PASS lib_i2c::i2c_master_sim_tests::clock_stretch[speed=400;stop=stop;arch=xs1] PASS lib_i2c::i2c_master_sim_tests::clock_stretch[speed=400;stop=no_stop;arch=xs1] PASS lib_i2c::i2c_master_sim_tests::clock_stretch[speed=400;stop=stop;arch=xs2] PASS lib_i2c::i2c_master_sim_tests::clock_stretch[speed=400;stop=no_stop;arch=xs2] PASS lib_i2c::i2c_master_sim_tests::reg_ops_test[arch=xs1] PASS lib_i2c::i2c_master_sim_tests::reg_ops_test[arch=xs2] PASS lib_i2c::i2c_master_sim_tests::reg_ops_nack_test[arch=xs1] FAIL lib_i2c::i2c_master_sim_tests::reg_ops_nack_test[arch=xs2] PASS lib_i2c::i2c_master_sim_tests::repeated_start[arch=xs1] PASS lib_i2c::i2c_master_sim_tests::repeated_start[arch=xs2] PASS lib_i2c::i2c_master_sim_tests::single_port_test[speed=400;stop=stop] PASS lib_i2c::i2c_master_sim_tests::single_port_test[speed=100;stop=stop] PASS lib_i2c::i2c_master_sim_tests::single_port_test[speed=10;stop=stop] PASS lib_i2c::i2c_master_sim_tests::single_port_test[speed=400;stop=no_stop] PASS lib_i2c::i2c_master_sim_tests::single_port_test[speed=100;stop=no_stop] PASS lib_i2c::i2c_master_sim_tests::single_port_test[speed=10;stop=no_stop] PASS

60/61 PASSED

[pthedinger]

I believe I've addressed your comments, but please take a look and add more.