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Sample rate conversion library
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Bug in lib_src/examples/AN00231_ASRC_SPDIF_TO_DAC/src/block_serial.xc #29

Open ffomich opened 6 years ago

ffomich commented 6 years ago

This example code produces N*samples shift between left & right output channels.

For example, after ASRC 48kHz->48kHz the left channel is ahead of the right one by 1 sample.

Bug fix: in the function void serial2block(server serial_transfer_push_if i_serial_in, client block_transfer_if i_block_transfer[ASRC_N_INSTANCES], server sample_rate_enquiry_if i_input_rate)

if (chan_idx == ASRC_CHANNELS_PER_INSTANCE - 1) buff_idx++; //Move index when all channels received

MUST be

if (chan_idx == ASRC_CHANNELS_PER_INSTANCE) buff_idx++; //Move index when all channels received

ed-xmos commented 6 years ago

Thanks for taking the time to feedback.

I have looked at your suggestion. I can see that it would swap channels for the case where ASRC_CHANNELS_PER_INSTANCE = 1 but for ASRC_CHANNELS_PER_INSTANCE = 2 (for example 2 x low rate ASRC in a single task which is valid) it would break because chan_idx is either 0 or 1 (left, right) and so the buffer would never fill.

I assume you tested this in hardware and it fixed the issue? I suspect there is a channel swap/delay elsewhere in the code that this modification is correcting. Does that make sense?

ffomich commented 6 years ago

Hello, I added ASRC code from this example into the XMOS USB Audio project. Signal path is AES IN->ASRC->USB rec. I tested my project in hardware. Using original ASRC example code I always had 1 sample shift between left and right channels after ASRC 48->48. After this bug fix sample shift became 0. It looked like issue is fixed. But now after some time of testing sample shift=8 appear sometimes.