AN00202 main.xc comment and code conflict

[ahogen]

In main.xc of AN00202 (click here) the code comment states we are selecting the 24.576KHz clock. The code doesn't seem to line up with what the xCORE-200 Multichannel Audio board documentation says. I'm not sure which one it's supposed to be as, from what I understand, the PLL used could be factory programmed either way.

// Select 48Khz family clock (24.576Mhz)
mclk_select.output(0);                // <---- ?
pll_select.output(1);

[larry-xmos]

MCLK_FSEL 0 will indeed select 22.5792MHz. But PLL_SELECT 1 means we don't use CLK1 from the PL611, instead we use output of the CS2100 PLL.

I will correct the comment

[larry-xmos]

Thanks for the report