Create a ASRC demo example

[shuchitak]

Create a I2S Slave + pipeline example with the bclk and mclk in different clock domains and use the ASRC module to demonstrate sampling rate conversion when the input and output are in different clock domains.

[shuchitak]

My plan is to first create a simple application derived from the FFVA example to do this:

After this: Change mic_array to output 48KHz. Change I2S sampling rate to 96KHz Replace SRC with ASRC, heavily borrowing from the https://github.com/xmos/lib_src/tree/develop/examples/AN00231_ASRC_SPDIF_TO_DAC example for the rate_server implementation.

[mbanth]

@shuchitak, please provide a Story Point value for this issue. Thanks.

[mbanth]

This issue duplicates Jira AP-87.