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The RTOS HW test setup loops a 1v8 pin into a 3v3 pin #467

Closed ed-xmos closed 2 years ago

ed-xmos commented 2 years ago

The loopback: GPIO I/O X1D12 : X1D39

connects an IO on VIOL (3v3) to VDD18 (1v8). The GPIO test in test HIL drives from 1v8 to 3v3 which will not cause harm but result in an unreliable high input.

I found the issues when looping back the UART and driving 1Mbps @3v3 into a 1v8 port caused the chip to crash!

A series resistor and ensuring you drive X1D39-> X1D12 might be a quick work around.

xmos-jmccarthy commented 2 years ago

This rtos_driver hil tests are split across 2 apps currently. We should move the GPIO test from rtos_drivers/hil to the rtos_driver/hil_add application, and move it to a different connection. In both cases we should remove this jumper to prevent someone in the future from driving VDDIOL to VDD18.

This update should be 1 story point.

Another option would be to depopulate R35 and R37, and populating R36 and R38. With this change all IO would be on the 1V8 power rail, and give us access to these 1b ports for intertile IO tests.

ed-xmos commented 2 years ago

Some notes from a conversation with Joe: The data sheet says minimum voltage for a '1' is 3v3 is 0.65 VDDIO which is 2.145V. However we have measured closer to 1.3V (when Schmitt is off) although this is not guaranteed. This explains why the current setup works on the bench.

Driving the other way round will result in the clamp diodes start to conduct. 1.8V IOs are 2.1V max per the datasheet. You would need to use a very high value series resistor such as 100k, which with 25pF load you get a time constant of 2.5us which is large compared with the bit period of 1us as needed with HIL component testing such as UART. So this approach would only be suitable for low speed IO (tens of kilobits maybe).