Open freqmod opened 5 years ago
From reply to email to fairwaves: It seems it's related to https://github.com/xtrx-sdr/images/issues/37 (solution https://devtalk.nvidia.com/default/topic/770634/jetson-tk1/large-coherent-dma-blocks/) Have you tried to increase the coherent DMA pool? It works on most ARM platforms.
-- Using a command line with "pci=noaer vmalloc=512M cma=64M coherent_pool=32M" passes the DMA test, however both test_xtrx and sdrangel does not display any useful data (it does not seem like the buffer is written to from xtrx). However enabling #define VA_DMA_ADDR_FIXUP in xtrx.c in the kernel driver causes proper data to be delivered.
When i get overflows (both with sdrangel and test_xtrx) i get 16:08:26.704863 WARN: [XTRX] PCI:/dev/xtrx0: Total=65536 Processed=0 UserTotal=32768 UserProcessed=0 BUFTS=617644032+0 OURTS=611467264 16:08:26.717247 INFO: [BPCI] PCI:/dev/xtrx0: BUF_OVF TS:618168320 WTS:620153931 WTS_NXT:620167168 TS_NXT:624361472 SKIP 378 buffers INT_S:0 16:08:26.717335 INFO: [CTRL] PCI:/dev/xtrx0: Placing TC @624361472 on 0 data: 0 stat:3d Then i have to reboot to get xtrx to work again.
Hi
I am trying to make XTRX work with the NVIDIA jetson nano. I have gotten it to work somewhat (if somebody else have problems with lots of messages from PCI add "pci=noaer" to kernel boot), but i still have some problems with DMA buffers.
Due to limited memory i have to reduce the number of DMA buffers and buffer sizes from 32 to 14 in:
another option is to keep the buffer amount and reduce the sizes, but i haven't gotten that to work as well as the current approach.
With this i manage to get the test working, and for low samplerate for several tens of seconds. The problem is when i am not able to retrieve the buffers fast enough overflow handling is wrong. 14:44:57.798698 ERROR: [BPCI] PCI:/dev/xtrx0: Incorrect DMA pointers! (bufno=42 bufno_rd=25 rdidx=25 icnt=3)
The question i have is if it is possible to reduce the amount of used DMA buffers without recompiling the FPGA image? If i have to recompile the FPGA image are the sources available?