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Pre-built XTRX packages and firmware images
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TX DMA doesn't seem to work #54

Closed yahoo2016 closed 5 years ago

yahoo2016 commented 5 years ago

RX DMA seems working for Jetson TX2 by "./test_xtrx -t -l2", TX DMA locks TX2 when running "./test_xtrx -T".

I tried low level DMA tests using libxtrxll, RX DMA appears working (I got about 100MB/s), TX DMA doesn't seem working. The "xtrxll_dma_tx_post" function always returns 0, the log is below and the simplified test code from "test_xtrxll.c" is attached.

nvidia@tegra-ubuntu:~/xtrx/images/sources/build/libxtrxll/tests$ ./test_tx -l9 08:52:36.158175 DEBUG: xtrxllpciev0_discovery:264 [PCIE] pcie: Found pcie:///dev/xtrx0 08:52:36.183025 REGS: internal_xtrxll_reg_in:156 [PCIE] PCI:/dev/xtrx0: Read [001a] = 04000113 08:52:36.183092 INFO: xtrxll_base_dev_init:1124 [CTRL] PCI:/dev/xtrx0: XTRX Rev4 (04000113) 08:52:36.183136 INFO: xtrxllpciebase_dma_start:536 [BPCI] PCI:/dev/xtrx0: RX DMA STOP MIMO (BLK:0 TS:0); TX DMA STOP MIMO @0.0 08:52:36.183183 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [000d] = c0000000 08:52:36.183216 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [000d] = 42000000 08:52:36.183243 INFO: xtrxllpciev0_open:360 [PCIE] PCI:/dev/xtrx0: Device pcie:///dev/xtrx0 was opened 08:52:36.183284 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0000] = 002fffff 08:52:36.183323 DEBUG: xtrxllpciev0_lms7_spi_bulk:197 [PCIE] PCI:/dev/xtrx0: SPI[0/1] I:1 08:52:36.183354 REGS: internal_xtrxll_reg_in:156 [PCIE] PCI:/dev/xtrx0: Read [0000] = 00000000 08:52:36.183381 DEBUG: xtrxllpciev0_lms7_spi_bulk:203 [PCIE] PCI:/dev/xtrx0: SPI[0/1] 002fffff => 00000000 Detected LMS #0: 00000000 flags 0 0, txdma = 1 packetsz = 16384 08:52:36.190427 DEBUG: xtrxllpciev0_dma_tx_init:595 [PCIE] PCI:/dev/xtrx0: DMA TX mmaped to 0x7f886af000 08:52:36.190477 INFO: xtrxllpciebase_dma_start:536 [BPCI] PCI:/dev/xtrx0: RX DMA SKIP MIMO (BLK:0 TS:0); TX DMA 8 bit MIMO @0.0 08:52:36.190500 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [000d] = 80000001 08:52:36.191928 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 00000001 08:52:36.191966 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 00|00/00/00/00 RESET:0 Full:0 TxS:1 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000001f [00000001] 08:52:36.192006 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 0 TS 0 SAMPLES 4096 08:52:36.192030 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0008] = 00001000 08:52:36.192051 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.192086 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 01000111 08:52:36.192108 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 01|01/00/01/00 RESET:0 Full:2 TxS:1 00/00 FE:0 FLY:2 D:0 TS:0 CPL:0000001a [01000111] 08:52:36.192136 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 1 TS 0 SAMPLES 4096 08:52:36.192160 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.192197 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 02004221 08:52:36.192218 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 02|02/00/02/01 RESET:0 Full:4 TxS:1 00/00 FE:0 FLY:2 D:0 TS:0 CPL:0000021a [02004221] 08:52:36.192246 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 2 TS 0 SAMPLES 4096 08:52:36.192271 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.192308 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 03008331 08:52:36.192326 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 03|03/00/03/02 RESET:0 Full:6 TxS:1 00/00 FE:0 FLY:2 D:0 TS:0 CPL:0000041a [03008331] 08:52:36.192357 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 3 TS 0 SAMPLES 4096 08:52:36.192379 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.192414 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 0400c344 08:52:36.192434 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 04|04/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000061b [0400c344] 08:52:36.192460 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 4 TS 0 SAMPLES 4096 08:52:36.192482 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.192514 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 0500c344 08:52:36.192536 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 05|05/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [0500c344] 08:52:36.192562 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 5 TS 0 SAMPLES 4096 08:52:36.192579 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.192612 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 0600c344 08:52:36.192634 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 06|06/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [0600c344] 08:52:36.192661 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 6 TS 0 SAMPLES 4096 08:52:36.192679 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.192717 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 0700c344 08:52:36.192737 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 07|07/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [0700c344] 08:52:36.192764 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 7 TS 0 SAMPLES 4096 08:52:36.192786 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.192822 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 0800c344 08:52:36.192843 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 08|08/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [0800c344] 08:52:36.192871 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 8 TS 0 SAMPLES 4096 08:52:36.192896 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.192929 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 0900c344 08:52:36.192950 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 09|09/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [0900c344] 08:52:36.192976 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 9 TS 0 SAMPLES 4096 08:52:36.192997 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.193031 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 0a00c344 08:52:36.193052 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 10|10/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [0a00c344] 08:52:36.193078 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 10 TS 0 SAMPLES 4096 08:52:36.193105 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.193139 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 0b00c344 08:52:36.193160 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 11|11/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [0b00c344] 08:52:36.193187 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 11 TS 0 SAMPLES 4096 08:52:36.193208 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.193240 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 0c00c344 08:52:36.193261 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 12|12/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [0c00c344] 08:52:36.193287 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 12 TS 0 SAMPLES 4096 08:52:36.193308 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.193343 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 0d00c344 08:52:36.193359 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 13|13/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [0d00c344] 08:52:36.193389 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 13 TS 0 SAMPLES 4096 08:52:36.193411 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.193443 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 0e00c344 08:52:36.193465 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 14|14/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [0e00c344] 08:52:36.193494 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 14 TS 0 SAMPLES 4096 08:52:36.193516 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.193550 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 0f00c344 08:52:36.193572 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 15|15/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [0f00c344] 08:52:36.193595 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 15 TS 0 SAMPLES 4096 08:52:36.193619 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.193654 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1000c344 08:52:36.193671 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 16|16/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1000c344] 08:52:36.193767 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 16 TS 0 SAMPLES 4096 08:52:36.193795 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.193824 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1100c344 08:52:36.193842 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 17|17/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1100c344] 08:52:36.193865 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 17 TS 0 SAMPLES 4096 08:52:36.193882 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.193907 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1200c344 08:52:36.193925 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 18|18/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1200c344] 08:52:36.193947 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 18 TS 0 SAMPLES 4096 08:52:36.193964 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.193992 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1300c344 08:52:36.194009 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 19|19/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1300c344] 08:52:36.194030 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 19 TS 0 SAMPLES 4096 08:52:36.194049 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.194077 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1400c344 08:52:36.194093 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 20|20/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1400c344] 08:52:36.194117 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 20 TS 0 SAMPLES 4096 08:52:36.194131 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.194148 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1500c344 08:52:36.194160 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 21|21/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1500c344] 08:52:36.194175 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 21 TS 0 SAMPLES 4096 08:52:36.194187 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.194205 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1600c344 08:52:36.194216 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 22|22/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1600c344] 08:52:36.194231 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 22 TS 0 SAMPLES 4096 08:52:36.194244 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.194262 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1700c344 08:52:36.194273 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 23|23/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1700c344] 08:52:36.194289 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 23 TS 0 SAMPLES 4096 08:52:36.194301 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.194318 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1800c344 08:52:36.194329 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 24|24/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1800c344] 08:52:36.194344 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 24 TS 0 SAMPLES 4096 08:52:36.194357 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.194375 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1900c344 08:52:36.194387 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 25|25/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1900c344] 08:52:36.194403 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 25 TS 0 SAMPLES 4096 08:52:36.194415 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.194432 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1a00c344 08:52:36.194445 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 26|26/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1a00c344] 08:52:36.194476 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 26 TS 0 SAMPLES 4096 08:52:36.194494 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.194518 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1b00c344 08:52:36.194533 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 27|27/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1b00c344] 08:52:36.194552 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 27 TS 0 SAMPLES 4096 08:52:36.194566 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.194589 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1c00c344 08:52:36.194607 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 28|28/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1c00c344] 08:52:36.194624 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 28 TS 0 SAMPLES 4096 08:52:36.194649 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.194669 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1d00c344 08:52:36.194685 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 29|29/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1d00c344] 08:52:36.194708 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 29 TS 0 SAMPLES 4096 08:52:36.194726 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.194753 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1e00c344 08:52:36.194769 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 30|30/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1e00c344] 08:52:36.194790 DEBUG: xtrxllpciebase_dmatx_post:234 [BPCI] PCI:/dev/xtrx0: TX DMA POST 30 TS 0 SAMPLES 4096 08:52:36.194807 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [0009] = 00000000 dma_tx_post 0 08:52:36.194834 REGS: internal_xtrxll_reg_in_n:137 [PCIE] PCI:/dev/xtrx0: Read [0008+4] = 1f00c344 08:52:36.194850 DEBUG: xtrxllpciebase_dmatx_get:312 [BPCI] PCI:/dev/xtrx0: TX DMA STAT 31|31/00/03/03 RESET:0 Full:8 TxS:4 00/00 FE:0 FLY:3 D:0 TS:0 CPL:0000081f [1f00c344] 08:52:37.193812 INFO: xtrxllpciebase_dma_start:536 [BPCI] PCI:/dev/xtrx0: RX DMA SKIP MIMO (BLK:0 TS:0); TX DMA STOP MIMO @0.0 08:52:37.193924 REGS: internal_xtrxll_reg_out:147 [PCIE] PCI:/dev/xtrx0: Write [000d] = 80000000 Packets 31 took 1.001896 sec -- 0.483 MB/s (res=-16) 08:52:37.194131 DEBUG: xtrxllpciev0_dma_tx_deinit:617 [PCIE] PCI:/dev/xtrx0: DMA TX unmmaped

test_tx.c.zip

yahoo2016 commented 5 years ago

For ARM CPUs such as Nvidia Jetson TX2, SMMU needs to be disabled or driver needs to be modified. Nvidia does not recommend disable SMMU for security reasons.

yahoo2016 commented 5 years ago

For ARM CPUs such as Nvidia Jetson TX2, SMMU needs to be disabled or driver needs to be modified. Nvidia does not recommend disable SMMU for security reasons.