RISC vs CISC: has proven a smaller instruction set can usually be more efficient =>
Next performance boost may very well from domain specific architectures (DSA), specific hardware for a domain instead of a general purpose hardware, eg. GPUs for videos, DL chips =>
A parallel can be drawn with software: domain-specific languages (DSL) is similar to RISC, smaller feature set, but coupled with DSA, will achieve great performance boost. "DSA/DSL codesign". eg. TPU + TensorFlow
However to do all this we need a framework of tools:
how to quickly prototype hardware, in a software-y way ("programmable hardware", "agile hardware development"); with good benchmarks
RISC-V as open ISA
how to create DSL fast, and make them easy to learn (MLIR); is this similar to make languages as "libraries" today?
Without these we may go back to the old days where everyone's building their own hardware and software from scratch (without any reusable parts) hence expensive, fragmented.
Some quick notes:
RISC vs CISC: has proven a smaller instruction set can usually be more efficient => Next performance boost may very well from domain specific architectures (DSA), specific hardware for a domain instead of a general purpose hardware, eg. GPUs for videos, DL chips => A parallel can be drawn with software: domain-specific languages (DSL) is similar to RISC, smaller feature set, but coupled with DSA, will achieve great performance boost. "DSA/DSL codesign". eg. TPU + TensorFlow
However to do all this we need a framework of tools:
Without these we may go back to the old days where everyone's building their own hardware and software from scratch (without any reusable parts) hence expensive, fragmented.
AWS has FPGA instances!
References