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yaqwsx / KiKit

Automation tools for KiCAD
https://yaqwsx.github.io/KiKit
MIT License
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If you have custom rules that include a # comment in them, they will cause kikit to error. #605

Closed loki42 closed 10 months ago

loki42 commented 10 months ago

Prerequisites

KiKit version

kikit, version 1.4.0

KiCAD version

Version: 7.0.8-7.0.8~ubuntu20.04.1, release build

Operating system

ubuntu20.04

Description

If you have custom rules that include a # comment in them, they will cause kikit to error.

kikit panelize test.kicad_pcb test_panel.kicad_pcb An error occurred: Expected '(', got '#' No output files produced

Application: KiCad PCB Editor x86_64 on x86_64

Libraries: wxWidgets 3.2.1 FreeType 2.10.1 HarfBuzz 6.0.0 FontConfig 2.13.1 libcurl/7.68.0 OpenSSL/1.1.1f zlib/1.2.11 brotli/1.0.7 libidn2/2.2.0 libpsl/0.21.0 (+libidn2/2.2.0) libssh/0.9.3/openssl/zlib nghttp2/1.40.0 librtmp/2.3

Platform: Ubuntu 20.04.6 LTS, 64 bit, Little endian, wxGTK, ubuntu, x11

Build Info: Date: Sep 30 2023 13:54:09 wxWidgets: 3.2.1 (wchar_t,wx containers) GTK+ 3.24 Boost: 1.71.0 OCC: 7.5.2 Curl: 7.88.1 ngspice: 38 Compiler: GCC 9.4.0 with C++ ABI 1013

Build settings: KICAD_SPICE=ON

Steps to Reproduce

Add these customs rules, they validate correctly.

(version 1)
#Kicad 7

# 2-layer, 1oz copper
(rule "Minimum Trace Width (outer layer)"
    (constraint track_width (min 5mil))
    (layer outer)
    (condition "A.Type == 'track'"))

(rule "Minimum Trace Spacing (outer layer)"
    (constraint clearance (min 5mil))
    (layer outer)
    (condition "A.Type == 'track' && B.Type == A.Type"))

# 4-layer
(rule "Minimum Trace Width and Spacing (inner layer)"
    (constraint track_width (min 3.5mil))
    (layer inner)
    (condition "A.Type == 'track'"))

(rule "Minimum Trace Spacing (inner layer)"
    (constraint clearance (min 3.5mil))
    (layer inner)
    (condition "A.Type == 'track' && B.Type == A.Type"))

# silkscreen (Kicad 7 only)
(rule "Minimum Text"
    (constraint text_thickness (min 0.15mm))
    (constraint text_height (min 1mm))
    (layer "?.Silkscreen"))

(rule "Pad to Silkscreen"
    (constraint silk_clearance (min 0.15mm))
    (layer outer)
    (condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))

# edge clearance
(rule "Trace to Outline"
    (constraint edge_clearance (min 0.3mm))
    (condition "A.Type == 'track'"))

# This would override board outline and milled areas
#(rule "Trace to V-Cut"
#   (constraint clearance (min 0.4mm))
#   (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'"))

# drill/hole size
(rule "drill hole size (mechanical)"
    (constraint hole_size (min 0.2mm) (max 6.3mm)))

(rule "Minimum Via Hole Size"
    (constraint hole_size (min 0.2mm))
    (condition "A.Type == 'via'"))

(rule "Minimum Via Diameter"
    (constraint via_diameter (min 0.45mm))
    (condition "A.Type == 'via'"))

(rule "PTH Hole Size"
    (constraint hole_size (min 0.2mm) (max 6.35mm))
    (condition "A.isPlated()"))

(rule "Minimum Non-plated Hole Size"
    (constraint hole_size (min 0.5mm))
    (condition "A.Type == 'pad' && !A.isPlated()"))

(rule "Minimum Castellated Hole Size"
    (constraint hole_size (min 0.6mm))
    (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))

# clearance
(rule "hole to hole clearance (different nets)"
    (constraint hole_to_hole (min 0.5mm))
    (condition "A.Net != B.Net"))

(rule "via to track clearance"
    (constraint hole_clearance (min 0.254mm))
    (condition "A.Type == 'via' && B.Type == 'track'"))

(rule "via to via clearance (same nets)"
    (constraint hole_to_hole (min 0.254mm))
    (condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))

(rule "pad to pad clearance (with hole, different nets)"
    (constraint hole_to_hole (min 0.5mm))
    (condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))

(rule "pad to pad clearance (without hole, different nets)"
    (constraint clearance (min 0.127mm))
    (condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))

(rule "NPTH to Track clearance)"
    (constraint hole_clearance (min 0.254mm))
    (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))

(rule "PTH to Track clearance)"
    (constraint hole_clearance (min 0.33mm))
    (condition "A.isPlated() && A.Type != 'via' && B.Type == 'track'"))

(rule "Pad to Track clearance)"
    (constraint clearance (min 0.2mm))
    (condition "A.isPlated() && A.Type != 'via' && B.Type == 'track'"))

kikit panelize test.kicad_pcb test_panel.kicad_pcb

yaqwsx commented 10 months ago

Fixed in c651182