build verilog error.

[lishangli]

unning with RISCV=/root/chipyard/esp-tools-install mkdir -p /root/chipyard/sims/vcs/generated-src/chipyard.TestHarness.TramSoCConfig cd /root/chipyard && java -Xmx8G -Xss8M -XX:MaxPermSize=256M -Djava.io.tmpdir=/root/chipyard/.java_tmp -jar /root/chipyard/generators/rocket-chip/sbt-launch.jar -Dsbt.sourcemode=true -Dsbt.workspace=/root/chipyard/tools ";project chipyard; runMain chipyard.Generator --target-dir /root/chipyard/sims/vcs/generated-src/chipyard.TestHarness.TramSoCConfig --name chipyard.TestHarness.TramSoCConfig --top-module chipyard.TestHarness --legacy-configs chipyard:TramSoCConfig" OpenJDK 64-Bit Server VM warning: Ignoring option MaxPermSize; support was removed in 8.0 [info] welcome to sbt 1.4.9 (Ubuntu Java 11.0.20.1) [info] loading settings for project chipyard-build from plugins.sbt ... [info] loading project definition from /root/chipyard/project [error] [/root/chipyard/build.sbt]:329: illegal start of simple expression [error] [/root/chipyard/build.sbt]:337: ')' expected but eof found. [warn] Project loading failed: (r)etry, (q)uit, (l)ast, or (i)gnore? (

How to solve with the problem?

[yhqiu16]

There seem to be some syntax errors in the build.sbt. You may try to solve the errors at first and retry the building.

[lishangli]

Thank you for your reply. I have resolved this issue, but there are still some code issues when generating Verilog. I have already resolved some of them by https://github.com/ucb-bar/chipyard/pull/1052/commits/7d244d635c5f02512e8e9a3d2c0a057fdd4b0bd1#diff -76c003eb0146c4fb67087906e1cf832fbd5d6df982947ffe68b77bf591614722. there are still some unresolved issues: [error] /root/chipyard/generators/fdra/cgra-mg/src/main/scala/soc/LoadController.scala:162:21: too many arguments (6) for constructor Queue: (gen: T, entries: Int, pipe: Boolean, flow: Boolean)(implicit compileOptions: chisel3.CompileOptions)chisel3.util.Queue[T] [error] false, false, false, true)) [error] ^ [error] /root/chipyard/generators/fdra/cgra-mg/src/main/scala/soc/MultiPortTLB.scala:130:10: value prv is not a member of Chisel.Bundle{val req: chisel3.util.DecoupledIO[freechips.rocketchip.rocket.TLBReq]; val resp: freechips.rocketchip.rocket.TLBResp; val sfence: chisel3.util.Valid[freechips.rocketchip.rocket.SFenceReq]; val ptw: freechips.rocketchip.rocket.TLBPTWIO; val kill: Chisel.Bool} [error] tlb.io.prv := req.status.prv [error] ^ [error] /root/chipyard/generators/fdra/cgra-mg/src/main/scala/soc/MultiPortTLB.scala:131:19: value v is not a member of freechips.rocketchip.rocket.TLBReq [error] tlb.io.req.bits.v := false.B [error] ^ [error] /root/chipyard/generators/fdra/cgra-mg/src/main/scala/soc/MultiPortTLB.scala:141:22: value hv is not a member of freechips.rocketchip.rocket.SFenceReq [error] tlb.io.sfence.bits.hv := false.B [error] ^ [error] /root/chipyard/generators/fdra/cgra-mg/src/main/scala/soc/MultiPortTLB.scala:142:22: value hg is not a member of freechips.rocketchip.rocket.SFenceReq [error] tlb.io.sfence.bits.hg := false.B [error] ^ [error] /root/chipyard/generators/fdra/cgra-mg/src/main/scala/soc/MultiPortTLB.scala:154:36: missing argument list for method fire in class Valid [error] Unapplied methods are only converted to functions when a function type is expected. [error] You can make this conversion explicit by writing fire _ or fire(_) instead of fire. [error] when (interrupt && tlb.io.sfence.fire) { [error] ^ [error] /root/chipyard/generators/fdra/cgra-mg/src/main/scala/soc/StoreController.scala:100:21: too many arguments (6) for constructor Queue: (gen: T, entries: Int, pipe: Boolean, flow: Boolean)(implicit compileOptions: chisel3.CompileOptions)chisel3.util.Queue[T] [error] false, false, false, true)) [error] ^ [error] /root/chipyard/generators/fdra/cgra-mg/src/main/scala/soc/TRAM.scala:5:8: value True is not a member of object firrtl.Utils [error] import firrtl.Utils.True [error] ^ [error] 8 errors found [error] (fdra / Compile / compileIncremental) Compilation failed