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yhqiu16 / NVMeCHA

NVMe Controller featuring Hardware Acceleration
GNU General Public License v3.0
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change the pciex8 to x4 which cased a firmware problem #7

Open preta21 opened 1 year ago

preta21 commented 1 year ago

Hello, I'm using NVMeCHA to adjust to my FPGA. Adjusted xdc, In PCIe x8, it works fine, However, the controller doesn't work after I changed PCIe Interface -> lane width to x4 in XDMA IP. image

I got these logs from uart

[12:16:59:577] ======NVMe Test Start========␊
[12:16:59:612] ␍NVMe Reg CC_EN is set␊
[12:17:13:792] ␍PS Set CSTS RDY ␊
[12:17:13:811] ␍Get cmd:␍␊
[12:17:13:884] E0006 0 0 0 0 0 0 0 0 0 7C2B0000 4 0 0 0 0 ␊
[12:17:13:931] Admin Command id is 14 ␍␊
[12:17:13:956] Admin Command(Identify), cid: 14, nsid: 0, cns: 0x0␊
[12:17:14:009] ␍Get cmd:␍␊
[12:17:14:021] 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ␊
[12:17:14:056] Admin Command id is 0 ␍␊
[12:17:14:081] Admin Command(Delete IO SQ), cid: 0, nsid: 0, qid: ======NVMe Test Start========␊
[12:17:14:166] ␍

It seems that the controller only received one Identify(Namespace data structure, cns=0x00) admin command, and shutdown. (the host deletes SQ; CC_EN and CSTS_RDY are not set.)

I modified the IP configure, and also changed the PL_LINK_CAP_MAX_LINK_WIDTH to 4 in nvme_top.v. So, is there anyting else I need to do when make a PCIe lane width modification?

Sincerely.

yhqiu16 commented 1 year ago

In your case, the data width will change from 256 to 128 bits, so you should adjust the interfaces in the data path accordingly. The PL_LINK_CAP_MAX_LINK_WIDTH is not a global parameter.