Please put the original license of DSAGEN back

[SihaoLiu]

Hello, It seems that this repo is a clone of dsa-framework, could you please put the original license back? https://github.com/PolyArch/dsa-framework/blob/master/LICENSE

Thank you

[tony-nowatzki]

This is actually really cool that you hacked our framework -- a shoutout to DSAGEN somewhere would be so much appreciated!

[yhtmp]

DSAGEN is indeed a great work, which has inspired us a lot for the architecture modeling and DFG mapping of our TRAM. We really appreciate that you have open-sourced this wonderful work, which is referred to in our paper ("TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework" @FPL2022). For the source codes, we wrote new codes from scratch for our TRAM, so this is definitely not a clone of dsa-framework. Some of our innovations are as follows.

1. We propose a novel general CGRA interconnect model that can unify the typical N2N, switch-based and CB-SB interconnects. The unified interconnect model combines the switch-based interconnect topology and the CB-SB connection flexibility. The rich and flexible design parameters enable the interconnect to provide sufficient connection flexibility to support large-scale CGRAs, similar to FPGAs with hundreds of routing tracks capable of supporting various applications. Moreover, the connection flexibility is parameterized to facilitate architectural optimization between connectivity and area. In contrast, the previous open-source CGRA with the CB-SB interconnect, namely AHA [21] could only support fully-connected CBs, which were extremely resource-consuming. Previous CGRAs with the switch-based interconnect generally have only one routing track and use crossbars to implement the interconnect, which have quite limited flexibility.
2. We propose a flexible CGRA template with rich design parameters including the size, interconnect type, track number, track and delay register number, and connection flexibility. These parameters facilitate architectural optimization between performance and area.
3. We propose a novel CGRA mapper that can support our unified interconnect model, capable of handling the spare connectivity inside GIBs. Besides, we present a novel critical-path-driven data synchronizer that can minimize the DFG latency.

To be specific, the main architecture difference from DSAGEN is as follows. We propose a novel unified interconnect model, which fuses the CB-SB connection flexibility that DSAGEN cannot provide. Besides, the connections of the switches, vector ports, and PE inputs in DSAGEN are all based on crossbar, which brings a specific property that all the input ports of a component are commutative. Therefore, your architecture modeling, ADG abstraction, and mapping are all dependent on this strict property. We eliminate this constraint and provide support for spare connections in GPEs and GIBs. In the mapping flow, we propose a novel critical-path-driven data synchronization which is decoupled with the graph-based PnR. The mapping performance can be further optimized with a simulated annealing (SA) algorithm that calls the PnR and synchronizer iteratively.

Again, we really appreciate that you made the great work, DSAGEN, open-source, which is based on the BSD-2 License. For our TRAM, we do not copy codes from DSAGEN and would like to use a new BSD-3 License. If there is any related issue, we can have further discussions.

P.S.: This is a temporary repository for blind review. We will move the source codes to our non-anonymous github later.

[tony-nowatzki]

Cool -- excited to see the paper at FPL22!

The code here is not an exact copy, of course, but also definitely not from scratch. : )

Maybe there is some misunderstanding...

[yhtmp]

Thanks for your feedback. The "from scratch" is not exact. We would like to add the notice as follows in our license: Parts of the codes refer to the dsa-framework, and retain the copyright: "Copyright (c) 2020, The University of California (Regents)".

Do you have any further feedback?