search

ymherklotz / verismith

Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
GNU General Public License v3.0
96 stars 12 forks source link

Add SystemVerilog parsers found in sv-tests? #77

Open mithro opened 4 years ago

mithro commented 4 years ago

Since SystemVerilog parsers are probably required to also parse Verilog, you might be interested in setting up verismith on the various parsers and tooling that are included in the System Verilog Compliance Test Suite.

I'm guessing you already have Yosys, Verilator and Icarus. It would be interesting to see if verismith provides any value to "just parsing tools" like https://github.com/google/verible (which is a SystemVerilog linter + formatter) or Surelog (which is a generic SystemVerilog frontend targeting both Yosys and Verilator through https://github.com/alainmarcel/UHDM

mithro commented 4 years ago

BTW My employer (Google) might be in the position of supplying academic grants to have you investigate verismith with Verible / Surelog. Feel free to contact me at tansell@google.com if that could be interesting to you.

ymherklotz commented 3 years ago

That is actually a really interesting proposition, it would be interesting to see if it could be adapted to test these tools and set it up on the Test Suite. The parser built into Verismith is actually built on top of the same parser as sv2v which seems to have good SystemVerilog coverage, so I was already interested in using sv2v as my frontend instead.

Are you proposing we should support the generation of SystemVerilog code and higher level constructs to test these tools? If it's a conversion from SystemVerilog to Verilog like sv2v I think that would be quite simple to verify, but frontends I am more unsure about. Would be nice to look into this further.

I am currently quite busy with a different project, but will soon be able to come back to this, I will definitely contact you soon about this though.