Use struct in systemverilog implementation

[yodalee]

Using struct basically make testbench implementation easier. The write_verilator_port becomes identical:

write_verilator_port(dut_wrapper.dut->in, verilog::pack(in));

[yodalee]

For record, this change will cause the dumped waveform more difficult to debug. The input/output data will become a long bits array, and difficult to distinguish real content. This issue can be mitigated by extract the struct to set of registers in the module.

[johnjohnlin]

looks good