Closed GoogleCodeExporter closed 9 years ago
A paper on the topic was taken as input:
Basic Performance Measurements for AMD Athlon™ 64,
AMD Opteron™ and AMD Phenom™ Processors by Paul J. Drongowski.
The event groups described there were as far as possible configured for the
core Processor architectures (Intel Nehalem, Core2, K8, K10).
This covers especially the Cache miss rate and ratios which give a good metric
on cache reuse and locality and are also employed by craypat.
The groups were tested with likwid-bench on plausibility.
Original comment by jan.trei...@gmail.com
on 6 Jul 2010 at 11:18
Original issue reported on code.google.com by
jan.trei...@gmail.com
on 28 Sep 2009 at 8:24