NVDLA

[ytgui]

http://nvdla.org/ http://nvdla.org/primer.html https://github.com/nvdla https://github.com/nvdla/hw

[ytgui]

Summary

1. The NVIDIA Deep Learning Accelerator (NVDLA)
2. A free and open architecture, promotes a standard way to design deep learning inference accelerators.
3. Modular architecture, scalable, highly configurable, designed to simplify integration and portability.
4. Supports a wide range of IoT devices.
5. Delivered as an open source project under the NVIDIA Open NVDLA License.
6. Proven hardware architecture, based on Xavier.
7. Complete solution, with a Verilog and C-model, Linux drivers, test benches and test suites, kernel- and user-mode software, and software development tools. Easily portable to other operating systems.

Architecture

1. Convolution Core – optimized high-performance convolution engine.
2. Single Data Processor – single-point lookup engine for activation functions.
3. Planar Data Processor – planar averaging engine for pooling.
4. Channel Data Processor – multi-channel averaging engine for advanced normalization functions.
5. Dedicated Memory and Data Reshape Engines – memory-to-memory transformation acceleration for tensor reshape and copy operations.

• The same NVDLA hardware architecture could serve a variety of implementation sizes.
• Each of these blocks are separate and independently configurable. (A system that has no need for pooling, for instance, can remove the planar averaging engine entirely; or, a system that needs additional convolutional performance can scale up the performance of the convolution unit without modifying other units in the accelerator.)
• Scheduling operations for each unit are delegated to a co-processor or CPU.

Software

NVDLA with Top-Level DL Lib

Directory

• hw/ (RTL, C-model, and testbench code)
  • vmod/nvdla/ - Verilog implementation of NVDLA
  • vmod/vlibs/ - Library and cell models
  • vmod/rams/ - Behavioral models of RAMs used by NVDLA
  • syn/ - Example synthesis scripts for NVDLA
  • perf/ - performance estimator spreadsheet for NVDLA
  • verif/ - Trace-player testbench for basic sanity validation
  • tools/ - Tools used for building the RTL and running simulation/synthesis/etc.
  • spec/ - RTL configuration option settings.
• sw/ (Kernel and user mode driver)
  • umd
  • kmd
  • script
  • regression

Problem

• 都 TM 公开了那怎么赢利，黄氏刀法使在哪里
  • 答：NVDLA is provided as a set of IP-core models -> 向 ARM 学习，不直接卖芯片了而是提供 IP 给用户自己集成。（目标可能是为了对抗类似寒武纪地平线平头哥一类的初创公司，这玩意生态发展起来后初创公司只能等死）

Reference

http://nvdla.org/sw/contents.html https://github.com/nvdla/sw