Run Z80 full speed when VIC-II is disabled

[idun-project]

I would think that the BA line could be used to control the Z80 clock, similarly to how you use the 1M CLK.

The advantage would be that when the VIC-II is disabled, as in "FAST" mode, the BA signal doesn't cycle. It should be asserted all the time because the bus is available all the time (ignoring expansion port DMA, for now). So could the Z80 CLK be gated by BA instead, and allow the Z80 to run at 8 MHz when the VIC-II is disabled, while still running at an effective 4 MHz when the ViC-II is enabled and BA is cycling...

[itsPkun]

The VIC-IIe is also, and more importantly, responsible for DRAM refresh. You would need to additionally watch the RAS and CAS lines to prevent the z80 from stomping all over memory refresh cycles.

[ytmytm]

If I'm not mistaken BA is connected (through some gates, possibly combining it with /DMA from exp. port) to Z80 /BUSRQ signal so Z80 (like 8500) stops when VIC needs additional cycles during badlines or to fetch sprite data.

This would give some extra cycles for Z80 during badline condition when VIC holds the bus during CPU cycles. That wouldn't benefit 80-column CP/M much, but it's an interesting idea.

As for allowing Z80 to run during VIC clock phase (running at 8MHz until memory access is requested instead of 8Mhz half of the time) - I was not able to solve this using a latch and GAL equations. It's easy to describe in software what needs to happen: if memory or I/O access is requested stop the Z80 (hold its clock or assert /WAIT) until next CLK1MHZ edge; then keep feeding it CLK1MHZ signal as clock until memory or I/O access is not needed anymore. But I just don't know how to put it into this simple hardware.