yupferris
commented
1 year ago It seems this crate has the restriction that all modules always operate in the same clock domain.
This is correct.
Are there any plans to remove this restriction? :)
Nope. Most (arguably well-formed) RTL design is synchronous within a certain clock domain with special-purpose modules used to communicate between them; kaze is meant to cover only the former, which mainly serves to simplify how the simulator works and its interface. AFAIR verilator and CXXRTL have the same restriction.
It should be possible to encode clock domains into signal/module types and have a simulator with a more limited interface that could support multiple clock domains, perhaps. But I have no further concrete thoughts about this and no intent on digging further in support of the projects I use kaze for.
Btw, do you have a recommendation which crate or HDL to use, for designing an asynchronous manycore CPU, where each core is self-clocked?
I personally only have experience doing multi-clock designs in (System)Verilog targeting FPGA, so I don't really know. But I think amaranth and chisel support it in limited capacity? Could be wrong, though. The only other really interesting Rust HDL project I'm aware of is Spade (which is a more fully-fleshed-out-HDL with richer types/syntax but lacking the metaprogramming facilities that you get with a meta/embedded-HDL) and from what I can tell that also only supports a single clock domain AFAIK.
Boscop
It seems this crate has the restriction that all modules always operate in the same clock domain. Are there any plans to remove this restriction? :)
Btw, do you have a recommendation which crate or HDL to use, for designing an asynchronous manycore CPU, where each core is self-clocked?